Specifications

QSSC-S4R Technical Product Specification Power Distribution Board (PDB)
115
*Provided by droop share and the loading only under static not apply to start-up, AC-Off and hot- swap
applications.
13.2.4 Dynamic Loading
The output voltages shall remain within limits specified in table above for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50Hz and 5 kHz at duty cycles
ranging from 10%-90%. The load transient repetition rate is only a test specification. The ' step load may occur
anywhere within the MIN load to the MAX load shown below.
Table 64. Transient Load Requirements
Output
Max ' Step Load Size
Max Load Slew Rate Test capacitive Load
+12VDC 60% of max load 0.25 A/us 2000uF
+3.3Vsb
4A (TBD) 0.25 A/us
20
P
F
Note: the +3.3Vsb ' step load 4A is for N+1 operation; ' step load 2A is for single module.
13.2.5 Protection Circuits
13.2.5.1 Over Current Protection (OCP)
The PS+PDB combo shall shutdown and latch off after an over current condition on the 2x4 HSBP fan power
connector occurs. This latch shall be cleared by toggling the PSON
#
signal or by an AC power interruption. The +12V
output from the PDB to the 2x4 HSBP fan power connector is limited to 240VA of power. There shall be a current
sensor and the circuit to shut down the entire PS+PDB combo if the limit is exceeded. Table 65. Over Current
Protection Limits / 240VA Protection contains the over current limits. The values are measured at the PDB harness
connectors. The PDB shall not be damaged from repeated power cycling in this condition.
Table 65. Over Current Protection Limits / 240VA Protection
Output Voltage
MIN OCP TRIP LIMITS MAX OCP TRIP LIMITS
12V 2x4 HSBP fan power
18.0A min 20A max
No other protection is required on the PDB.
13.2.6 Remote On/Off (PSON*)
The PSON
#
signal is required to remotely turn on/off the PS / PDB Combo. There is the PSON# Input receiving the
signal from the system and there is the PSON# Output signal leading from the PDB to each of the power supplies.
PSON
#
is a 5V TTL compatible, active low signal that turns on the +12V power rail of each PSs. When this signal is
not pulled low by the system, or left open, the 12V output is turned off. This signal is pulled HI to +3.3Vsb by a pull-up
resistor in the PDB.
13.2.7 PSKILL
The purpose of the PSKill pin is to allow for hot swapping of the power supply. The mating pin of this signal on the
PDB input connector should be tied to ground, and its resistance shall be less than 5 ohms.
13.2.8 POWER GOOD SIGNAL (PWOK)
PWOK is a Power Good, 3.3V TTL compatible, coming from the PS, active HI logic signal, which will be pulled HIGH
by the power supply to indicate that its +12V output is within its regulation limits. When its +12V output voltage falls
below regulation limits or when AC power has been removed for a time sufficiently long so that power supply operation
is no longer guaranteed, PWOK will be de-asserted to a LOW state.
13.2.9 SMBAlert#
This signal indicates that the power supplies are experiencing a problem that the user should investigate. The
SMBALERT# output signal going to the system (an interrupt) is the AND function of the following 8 logic signals: