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QSSC-S4R Technical Product Specification Contents

QSSC-S4R Technical Product Specification

Revision 1.0

September 14, 2010

Summary of content (322 pages)

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QSSC-S4R Technical Product Specification Contents QSSC-S4R Technical Product Specification Revision 1.
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Revision History Date Revision Number Modifications Sept. 14, 2010 1.0 First release Disclaimer Information in this document is provided in connection with Server System QSSC-S4R manufactured by Quanta Computer Inc. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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QSSC-S4R Technical Product Specification Contents Contents 1. Introduction .............................................................................................................................. 21 1.1 Document Organization .......................................................................................................................................... 21 1.2 System Overview...................................................................................................................
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3.3.5 Chassis Intrusion .............................................................................................................................................................. 53 4. Memory Riser .......................................................................................................................... 54 4.1 System Memory Topology and Functional Diagram .............................................................................................. 54 4.
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QSSC-S4R Technical Product Specification Contents 9.1 External Chassis Features – Front ......................................................................................................................... 76 9.1.1 Fan Subsystem ................................................................................................................................................................ 78 9.1.2 Operator Panel ..........................................................................................
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12.4.2 Output Current Rating .................................................................................................................................................. 106 12.4.3 Over- and Under-Voltage Protection ............................................................................................................................ 106 12.4.4 Short Circuit Protection ...............................................................................................................................
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QSSC-S4R Technical Product Specification Contents 16.1.12 Enhanced Intel SpeedStep® Technology................................................................................................................... 130 16.1.13 Intel® 64 Instruction Set Architecture (Intel® 64) ....................................................................................................... 130 16.1.14 Execute Disable Bit Feature ...........................................................................................
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18. BIOS Update Support......................................................................................................... 208 18.1 BIOS Update and Recovery ............................................................................................................................... 208 18.1.1 Performing BIOS Recovery .......................................................................................................................................... 208 18.2 OEM Binary ...................
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QSSC-S4R Technical Product Specification Contents 21.2.4 Logging Format Conventions ....................................................................................................................................... 241 21.3 POST Progress Codes and Errors ..................................................................................................................... 242 21.3.1 Diagnostic LEDs ......................................................................................................
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24.5.2 System Clock Synchronization ..................................................................................................................................... 261 24.6 System Event Log (SEL) .................................................................................................................................... 261 24.6.1 Servicing Events...................................................................................................................................................
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QSSC-S4R Technical Product Specification Contents 24.32.1 Backplane Types ........................................................................................................................................................ 284 24.33 LAN Leash Event Monitoring............................................................................................................................ 284 24.34 CATERR Reporting ............................................................................................
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29.1 Sensor Type Codes ............................................................................................................................................ 304 30. Hot-Swap Controller (HSC) Architecture ............................................................................ 313 30.1.1 I2C Interfaces ............................................................................................................................................................... 313 30.1.
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QSSC-S4R Technical Product Specification List of Figures List of Figures Figure 1 Main Board Block Diagram ................................................................................................................................. 23 Figure 2. Main Board Component Locations .................................................................................................................... 25 Figure 3 Intel® 7500 Chipset High-Level Block Diagram .....................................................
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Figure 38. Fan Location .................................................................................................................................................... 93 Figure 39. S4R Fan Module.............................................................................................................................................. 93 Figure 40. Fan Module Functional Block Diagram ...........................................................................................................
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QSSC-S4R Technical Product Specification List of Figures Figure 84. Setup Utility — Mass Storage Controller Configuration Screen .................................................................... 188 Figure 85. Setup Utility — Serial Port Configuration Screen .......................................................................................... 189 Figure 86. Setup Utility — USB Configuration Screen ...................................................................................................
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List of Tables Table 1. System Features................................................................................................................................................. 21 Table 2. Mainboard components ...................................................................................................................................... 26 Table 3. Intel® Xeon® 7500 processor key features ........................................................................................................
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QSSC-S4R Technical Product Specification List of Tables Table 39. Connector Descriptions .................................................................................................................................. 100 Table 40. COM Serial Port Connector Pin-out (External DB9 on Rear Panel), Pedestal .............................................. 101 Table 41. VGA Video Connector Pin-out ................................................................................................................
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Table 85. Memory RAS Configuration and State SEL Records for Memory Mirroring .................................................. 154 Table 86. Device Locator Nomenclature ........................................................................................................................ 155 Table 87. CPU Socket and Memory Board Grouping.................................................................................................... 155 Table 88.
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QSSC-S4R Technical Product Specification List of Tables Table 130. Setup Utility — Hard Disk Order Fields ........................................................................................................ 203 Table 131. Setup Utility — CDROM Order Fields .......................................................................................................... 203 Table 132. Setup Utility — CDROM Order Fields ..........................................................................................
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Table 176. System Status LED Indicator States ............................................................................................................ 258 Table 177. List of I2C Buses ........................................................................................................................................... 260 Table 178. FRU Device ID Map ......................................................................................................................................
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QSSC-S4R Technical Product Specification Introduction 1. Introduction Welcome to the QSSC-S4R Server System Technical Product Specification (TPS). This document contains detailed architecture and configuration information and describes hardware, BIOS, and BMC features. 1.1 Document Organization x Chapters1-14 provide information about the system hardware, board architecture and interfaces. x Chapters 15-22 describe the BIOS platform as implemented in the QSSC-S4R Server System.
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Introduction Front Control Panel and Operator Panel Rear I/O QSSC-S4R Technical Product Specification x BMC baseboard management controller x System power button and x Hard drive status LED LED x LAN1, LAN2, LAN3 and LAN4 status LEDs x System reset button x Video connector x NMI button x Three USB 2.
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QSSC-S4R Technical Product Specification Main Board 2. Main Board 2.1 Introduction The main board provides most of the basic functions for the system. Nearly all of the boards from the board-set plug into the main board. 2.1.1 Main Board Block Diagram Figure 1 Main Board Block Diagram The main board has the following features: x Board size: 16.3” x 18.65” x Intel® 7500 Chipset (Boxboro-EX IOH) and ICH10R components x Up to four Intel® Xeon® 7500, 6.4 GT/s, 5.86 GT/s and 4.
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Main Board QSSC-S4R Technical Product Specification x Four independent processor buses x Fully connected sockets (with 4 Intel® QuickPath interconnects per socket) x Several PCIe I/O subsystems x CPU-integrated memory controller x Registered DDR3 800/1066 MHz via on-board memory buffer (Intel® 7500 Scalable Memory Buffer) x RAS feature support: x CPU Sparing / Migration x Physical CPU hot add and remove x OS CPU on-lining (capacity change) x On-die error correction x Memory Demand and
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QSSC-S4R Technical Product Specification 2.1.2 Main Board Major Component Placement Figure 2.
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Main Board QSSC-S4R Technical Product Specification Table 2. Mainboard components Item A B C D E F G Component Type # Description 130W Intel® Xeon® 7500 series processor (Nehalem-EX) and CPU/socket 1–4 its next generation using Socket-LS (LGA 1567).
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QSSC-S4R Technical Product Specification H I J External USB IO Riser Slot SAS Riser Slot K Onboard SATA L Main Board Battery M N O P Q R S Internal USB header x2 Peripherals Front panel USB connector Memory Riser Slots FPFB Signal Connectors PDB Signal Connector PDB Power Connectors T BIOS Jumpers U ICH 10R Main Board Handle x2 CPLD Chips V W Main Board Rear: 2x4-pin double stacked USB2.
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Main Board QSSC-S4R Technical Product Specification 800/1067 memory technologies. It uses a power-through-the-pins power delivery system and LS socket. Some key features of the Intel® Xeon® 7500 processor are listed in Table 3. Table 3. Intel® Xeon® 7500 processor key features Feature Number of cores / threads per core Lowest-Level Cache (LLC) Physical Address Intel QuickPath Interconnect speeds 7500 processor 8/2 24 MB 44 bits 4.8/5.86/6.
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QSSC-S4R Technical Product Specification 2.2.1.4 Main Board Rbox: Intel® QuickPath Interconnect Router The Intel® Xeon® Rbox is an eight-port router, where each port is an 80-bit, single-flit-wide Intel QuickPath Interconnect port. Of the eight ports, four are connected to external Intel QuickPath Interconnect ports. The external ports are 20-bit lanes nominally running at 6.4 GT/s. The external Intel QuickPath Interconnects transmit via the pads and cross a clock domain into the uncore clock frequency.
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Main Board QSSC-S4R Technical Product Specification 2.2.2 Intel® 7500 Chipset The Intel® 7500 Chipset (Boxboro I/O Hub) component provides a connection point between various I/O components and Intel® QuickPath Interconnect (Intel® QPI) based processors. Intel® 7500 Chipset provides the following: y y y y y y 2.2.2.
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QSSC-S4R Technical Product Specification Main Board Figure 3 Intel® 7500 Chipset High-Level Block Diagram 2.2.2.2 Intel® QPI Features Two full-width Intel® QPI link interfaces: x Packetized protocol with 18 data/protocol bits and 2 CRC bits per link per direction x 4.8 GT/s, 5.86 GT/s and 6.4 GT/s supporting different routing lengths. x Fully-coherent write cache with inbound write combining x Read Current command support x Support for 64-byte cache-line size 2.2.2.
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Main Board QSSC-S4R Technical Product Specification x8. If that attempt fails, an attempt is made at x4, then at x2 and finally at x1. Note that the x8, x4 and x2 link widths will only use the LSB positions from lane 0, while a x1 link can be connect to any of the x positions (lane 0-3) providing a higher tolerance to single point lane failures. When settling on a narrower width, the remaining links are unused.
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QSSC-S4R Technical Product Specification Main Board Figure 14. QSSC-S4R Memory Riser Functional Block Diagram and DIMM Population Rules Intel® 7500 Scalable Memory Buffer (Mill Brook) Functionality” on page 54. 2.3.1 ICH10R Southbridge The Intel ICH10R incorporates a variety of PCI devices and functions. They are divided into seven logical devices. The first is the DMI-to-PCI bridge (Device 30).
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Main Board 2.3.1.1 QSSC-S4R Technical Product Specification Enterprise South Bridge Interface (ESI) Enterprise South Bridge Interface (ESI) is the chip-to-chip connection between the IOH and ICH10. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. 2.3.1.2 PCI Express ICH10 provides up to six PCI Express Gen1 root ports.
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QSSC-S4R Technical Product Specification Main Board The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818MHz oscillator input provides the clock source for these three counters. ICH10R provides an ISA-compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers.
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Main Board QSSC-S4R Technical Product Specification applications to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory. 2.3.1.16 System Management Bus (SMBus) ICH10R contains an SMBus host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.
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QSSC-S4R Technical Product Specification Main Board The main board includes a 300 pin PCI Express super-slot custom connector to interface with the I/O riser card.
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Main Board QSSC-S4R Technical Product Specification generates 100MHz SRC clocks including an input to a DB1200 buffer to I/O subsystems. Figure 4 shows which clocks are present in the system and what subsystems they serve. CK410B+ synthesizes and distributes a multitude of clock outputs at various frequencies, timings and drive levels using a single, 14.318MHz crystal. CK410B+ is PCI Express Gen2 & FBD2 compliant clock generator for Intel-based servers.
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QSSC-S4R Technical Product Specification Main Board Figure 4. Main Board Clock Block Diagram CK410B supports SSC (Spread Spectrum Clocking) and SRC’s (Serial Reference Clocks), and supplies the following clock outputs: x 4x 0.7V current-mode differential CPU pairs (processors, IOH QPI) (strapped to 133 MHz specific for Boxboro-EX platform). x 5x 0.7V current-mode differential 100MHz SRC pairs. x 4x PCI (33MHz.) x 3x free-running PCI (33MHz.) x 1x 48MHz. x 2x 14.318MHz reference 2.3.6.1.
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Main Board QSSC-S4R Technical Product Specification 2.3.6.1.2 DB1200 PCI Express Clock Buffer DB1200 Version 2.0 device with PCI Express Gen2 support. It provides outputs that have low cycle-to-cycle jitter, and low output-to-output skew. DB1200 supports one- to eight-output configuration, taking a spread or non-spread differential HCSL input from CK410B+ main clock, or any other differential HCSL pair. DB1200 can generate HCSL or LVDS outputs from 100 to 400MHz in PLL Mode or 33 to 400MHz in Bypass Mode.
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QSSC-S4R Technical Product Specification Main Board 2.3.10 Post Code LEDs Eight light emitting diodes are used to indicate the raw binary output of BIOS POST codes. Although the value sent to the POST Code LEDs may be the same as the port 80h value at times during the POST process, it is not guaranteed. Table 6 shows the correlation the POST Code bit to LED reference designator. Table 5.
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Main Board QSSC-S4R Technical Product Specification x After CPU and VTT VRs are enabled, as well as any memory riser presence signal asserted, a global VR enable is asserted for memory risers, SAS Backpanel, and SAS Riser. An additional output for IO Riser power enable will be asserted at the same time as the other adapters in the system. x A signal internal to the PLD representing a system-wide powergood signal will be asserted once all FRU powergood signals are asserted.
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QSSC-S4R Technical Product Specification Figure 7.
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Main Board QSSC-S4R Technical Product Specification 2.3.14 Reset and Powergood Diagram Figure 8.
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QSSC-S4R Technical Product Specification 2.3.15 Power Sequencing/Timing Diagrams Figure 9. Main Board Power Sequencing Diagram 2.3.
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Main Board QSSC-S4R Technical Product Specification Table 7.
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QSSC-S4R Technical Product Specification Main Board Server Management 3. Main Board Server Management 3.1 Introduction The QSSC-S4R Server Management consists of many embedded technologies. These technologies are a combination of the following: x Board instrumentation x Sensors x Interconnects x Server management controllers x Firmware algorithms x System BIOS The QSSC-S4R board set platform management system is based on the IPMI 2.0 Specification.
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Main Board Server Management QSSC-S4R Technical Product Specification x System event log (SEL) device functionality: The BMC supports and provides access to a SEL. x Sensor device record (SDR) repository device functionality: The BMC supports storage and access of system SDRs. x Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of sensors. It polls sensors to monitor and report system health.
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QSSC-S4R Technical Product Specification 3.2 Functional Architecture 3.2.1 Server Management Block Diagram Figure 10.
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Main Board Server Management QSSC-S4R Technical Product Specification 3.2.2 SMBus Block Diagram Figure 11.
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QSSC-S4R Technical Product Specification Main Board Server Management 3.2.3 Hardware Monitoring Block Diagram Figure 12. Hardware Monitoring Block Diagram 3.2.4 Sensor Data Record SDR (SDR) Repository The BMC implements a logical Sensor Data Record (SDR) repository device. The SDR repository is accessible via all communication transports, even while the system is powered off. 3.2.5 Field Replaceable Unit (FRU) Inventory Devices The BMC implements the interface for logical FRU inventory devices.
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Main Board Server Management 0E 0F 10 4 5 5 QSSC-S4R Technical Product Specification A6h AEh A8h Power Supply 4 Front Panel Fan Board SAS (Optional) RO RW RW 256 256 256 3.2.6 System Event Log (SEL) The BMC allocates memory space for logging system events. SEL events can range from critical system errors to basic system monitoring reports. The SEL can be cleared in the system BIOS setup, or by using the SEL viewer utility or Intel® System Management application. 3.2.
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QSSC-S4R Technical Product Specification x Main Board Server Management All 4x power supplies are not installed in the system OR multiple power supplies failed even though all 4x power supplies are installed (Don’t assert this signal with three or more functional power supplies). x AND Processor VR current trip point (default setting: 90% of supported TDP current) is triggered. x AND System power utilization is high and exceeds a pre-set limit of 80%.
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Memory Riser QSSC-S4R Technical Product Specification 4. Memory Riser The QSSC-S4R Server System supports up to eight memory riser modules that plug into the main board vertically via 230-pin PCIe type card edge connectors.
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QSSC-S4R Technical Product Specification Figure 14. QSSC-S4R Memory Riser Functional Block Diagram and DIMM Population Rules 4.2 Intel® 7500 Scalable Memory Buffer (Mill Brook) Functionality 4.2.1 Intel® Scalable Memory Interconnect Functionality Intel® SMI protocol and signaling includes support for the following: x 4.8 Gbs, 6.4 Gbs signaling forwarded clock fail-over NB and SB. x 9 data lanes plus 1 CRC lane plus 1 spare lane SB. x 12 data lanes plus 1 CRC lane plus 1 spare NB.
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Memory Riser QSSC-S4R Technical Product Specification 4.2.2 DDR3 Functionality Figure 15.
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QSSC-S4R Technical Product Specification Memory Riser 4.3 Functional Architecture Figure 16 Memory Riser Block Diagram 4.3.1 Supported Memory Configurations The following sections describe the memory configurations that are validated on the QSSC-S4R platforms. Table 10.
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Memory Riser QSSC-S4R Technical Product Specification x Sx - Indicates that the CPU socket is populated. S0 is CPU socket 1, S1 is CPU socket 2, S2 is CPU socket 3, and S3 is CPU socket 4. A Y indicates the CPU socket is populated. Blank indicates the CPU socket is empty. x S – Indicates whether the configuration supports the Spare mode of operation. Y indicates a Yes, N indicates a No. x Intra M – Indicates whether the configuration supports the Intra Mirroring mode of operation.
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QSSC-S4R Technical Product Specification I/O Riser 5. I/O Riser 5.1 I/O Riser Features The I/O riser board provides most of the systems rear I/O including four GbE LAN ports, serial and video connectors. In addition, the optional advanced server management upgrade kit with mounting and connections supports the Intel® RMM3 LAN management module. The I/O riser board supports the following features: y y y y y y y y y 59 Board size: 4.41” x 6.
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I/O Riser QSSC-S4R Technical Product Specification 5.2 Functional Architecture Figure 17. I/O Riser Block Diagram 5.3 Video Subsystem 5.3.1 Feature Overview The graphics controller is integrated in ServerEngines* Pilot II IBMC providing the onboard video interface.
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QSSC-S4R Technical Product Specification I/O Riser 5.3.2 ServerEngines Pilot II IBMC Block Diagram Figure 18. ServerEngines* Pilot II IBMC Block Diagram 5.3.3 Video Disable Feature BIOS can disable the video through a GPIO of ICH10R, which is connected to GPIO 21 of the Pilot II integrated baseboard management controller. BIOS will pull low FM_VIDEO_DISABLE_N After checking the disable video GPIO line BIOS POST_CMPLT, asserted by BIOS, BMC will disable the on-board video.
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I/O Riser QSSC-S4R Technical Product Specification Pilot includes two USB interfaces. The USB0 is a dedicated USB2.0 interface and the USB1 is the dedicated USB1.1 interface. These USB1 interface is used for PS2 to USB and remote Keyboard/Mouse interface. The USB2.0 is dedicated for remote storage devices y USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and floppy y USB 1.
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QSSC-S4R Technical Product Specification Intel® Remote Management Module 3 (RMM3) 6. Intel® Remote Management Module 3 (RMM3) This 1.23” x 2.30” x 0.062” thick printed circuit board is an external Ethernet management module which is designed to work with the IBMC (Integrated Baseboard Management Controller) enabling remote graphic server control via a builtin Web Console.
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Intel® Remote Management Module 3 (RMM3) y y QSSC-S4R Technical Product Specification Mouse tracking and synchronization. It allows remote viewing and configuration in pre-boot POST and BIOS setup. PCB size: 1.23-inch x 2.30-inch Refer to Intel® RMM3 Technical Product Specification or visit the links below for a detailed description of this board. Intel® RMM3 Technical Product Specification: http://www.intel.com/support/motherboards/server/sb/CS-030369.
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QSSC-S4R Technical Product Specification SAS Riser 7. SAS Riser 7.1 Introduction The SAS riser works in conjunction with the Hot-swap Backplane (HSBP) to give the end-user support for up to eight 2.5-inch SAS hard drives in a 4U chassis. The 6Gb SAS riser card is installed in the dedicated SAS Riser slot at the back of the system. This card is considered as a required FRU (Field Upgradable Unit) in the Enterprise SKU.
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SAS Riser QSSC-S4R Technical Product Specification Figure 20. SAS Riser Board System Block Diagram 7.2.1 I²C Interface The SAS Riser board contains three I2C busses that come from the SAS2108 ROC Controller. The SAS2108 I2C bus 0 is connected to a temperature sensor, the memory SPD SEEPROM, a 3-pin header, a PCA9551 or equivalent I2C LED driver and a PCA9546A or equivalent 4 port I2C switch.
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QSSC-S4R Technical Product Specification SAS Riser Figure 21. SAS Riser Board Placement View The sideband signals are configured to adhere to the SFF-8485 and SFF-8448 specifications. This dual sideband functionality allows the Hot-swap Backplane (HSBP) to determine the enclosure management type: either I2C or SGPIO. 7.2.4 Memory Interface The SAS Riser board supports a single bank of on-board DDR2 ECC memory at a speed of 800MHz.
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Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 8. Hot Swap Backplane (HSBP) 8.1 Introduction The Hot Swap Backplane (HSBP) provides several main functions for the system. Depending on whether the system has the SAS Riser installed, the HSBP supports up to eight 2.5-inch SAS/SATA hard drives – in the Enterprise SKU. Alternatively, when the system does not have the SAS Riser installed, the HSBP can also support up to six 2.
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QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 8.1.2 Placement View and LED Definition The following section describes major components and/or connectors located on the Hot-swap Backplane (HSBP). LED functionality is also described to provide an introduction to the HSBP board. Figure 22. HSBP – Front View and Hard Drive Connectors 0 – 7 Figure 23. HSBP – Rear View Table 12.
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Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification Table 14.
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QSSC-S4R Technical Product Specification 8.1.3.5 Hot Swap Backplane (HSBP) HSBP SGPIO Connectors Table 19. 1x6-pin HSBP SATA SGPIO A – Signal Description and Pin-outs Pin Signal Description SGPIO_SCLOCK_A SGPIO_SLOAD_A GND SGPIO_SATA_DETECT_N SGPIO_SDATAOUT0_A SGPIO_SDATAOUT1_A 1 2 3 4 5 6 NOTES: SGPIO_SATA_DETECT_N signal tied to GND on baseboard. Naming convention is with respect to baseboard (identical to pin-out used on the baseboard connector). Table 20.
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Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification Figure 24. HSBP System Block Diagram 8.2.1 SAS Buses The SAS buses are directly connected to the server board via the SAS RAID riser card that is plugged into the designated PCI-Express* slot on the server board. As a result, the SAS RAID riser card provides all SAS functionality and interfacing to the Hot Swap Backplane. 8.2.1.1 SAS Data SAS data between drives and server board are routed across two 4-port internal SAS cables.
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QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) 8.2.5 Vitesse* VSC410 Controller Functionality The Vitesse* VSC410 is a storage management controller with SCSI Accessed Fault-Tolerant Enclosure (SAF-TE) and SCSI enclosure services (SES). The figure below shows the Vitesse* VSC410 internal logic and external interfaces. Note that you need a SES I2C* cable which plugs into the SAS backplane/HSBP and the SAS adapter, in order to use the SES functions.
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Hot Swap Backplane (HSBP) QSSC-S4R Technical Product Specification 8.2.8 SAS Enclosure Management SAS enclosure management allows the Hot-swap Backplane to report SAS drive status and backplane temperature readings. A SAS RAID controller will interface with the enclosure management.
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QSSC-S4R Technical Product Specification Hot Swap Backplane (HSBP) AT24C64* 0xA0 VSC local bus Private SAS backplane FRU EEPROM TPM75 0x90 VSC local bus Private SAS backplane temperature sensor Table 23. Global I2C* bus Addresses (IPMB Bus) Device Address Bus Description VSC410* NA IPMB system interface VSC410* controller public IPMB bus 8.2.
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System Overview QSSC-S4R Technical Product Specification 9. System Overview QSSC-S4R is a 4U rack mount server that supports four CPU sockets (Intel® Xeon® 7500 series processors - up to 130W and its follow-on generation), 64 DDR3 registered DIMM modules, 10 PCIe cards, up to 8 2.5-inch SAS hard drives, one slim-line DVD RW, and an optional 5.25” tape device. The basic chassis structure is divided into a lower section and upper section.
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QSSC-S4R Technical Product Specification Item A B C D E F G System Overview Description Optical Drive Rear LAN LEDs (from I/O Riser) Operator Panel Video Connector USB 2.0 ports 5 ¼ - inch peripheral bay (SATA cable included in Enterprise SKU) 8 Hot swap hard drive bays Figure 28. Front Components (Enterprise SKU) Item Description A* Optical Drive Bay (empty) B Rear LAN LEDs (from I/O Riser) C Operator Panel D Video Connector E USB 2.
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System Overview x QSSC-S4R Technical Product Specification Control the front panel I/O providing the end user access to the system video, USB interfaces and LAN port LED indication and controlling the operator panel via a 2x6-pin connector. The front panel fan board (FPFB) supports the following features: x Board size: 13.6956” x 4.44” x Support up to eight 80mm hot swap fans x Front I/O: one VGA video port and three USB 2.
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QSSC-S4R Technical Product Specification System Overview The fans are docked on the front panel fan board (FPFB). Each fan module has an amber LED wired to the front panel fan board. The LED will turn on when the fan is not functioning within specifications. The fan module sends fan signals via a 2x3 connector to the front panel fan board (FPFB). Table 24. LED Definition Fan#1, 2, 3, 4, 5, 6, 7, 8 LED Color/Behavior Amber – On Off State Fan Failed Fan working correctly 9.1.
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System Overview QSSC-S4R Technical Product Specification Figure 32. System Rear (Enterprise SKU shown) Table 25. System rear items and descriptions Item A B Description SAS Riser Slot PCIe Gen-2x8, ½ length, x8 connector I/O Riser Quad Gigabit Ethernet Ports: Four LAN ports, RJ45 connector.
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QSSC-S4R Technical Product Specification System Overview NOTE: Refer to Tables below for maximum DC loading for both AC redundant and AC non redundant configurations. INSTALLATION REQUIREMENTS FOR AC REDUNDANT CONFIGURATIONS The minimum AC redundant configuration is with one PSU plugged into a main AC source, and the second PSU plugged into a separate AC source (e.g. UPS).
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System Overview QSSC-S4R Technical Product Specification Optical Device Yes Yes No 5.25” Tape Device Yes Yes No Power Supply 2+2 3+1 2+0 12V Available Power 1660W 2300W 1660W Power Redundancy AC/DC DC Only*** AC Only***** *Exclude SAS riser slot. **Some QRx4 configurations like > 32 DIMMs will have thermal limitations and so will throttle memory subsystem. ***Refer to “AC Redundant and Non-Redundant Operations” in the following section.
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QSSC-S4R Technical Product Specification System Overview protection circuitry for one of the outputs and a FRU EEPROM. It also routes PMBus I2C signals from the power supply modules to the system baseboard and vice versa. Refer to Section 13 “Power Distribution Board (PDB)” for a detailed description of the PDB. 9.
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System Overview Immunity Electrostatic discharge Acoustic QSSC-S4R Technical Product Specification Verified to comply with EN55024, CISPR 24, GOST-R Tested to ESD levels up to 15 kilovolts (kV) air discharge and up to 8 kV contact discharge without physical damage y Sound power: < 7.0 BA at ambient temperature < 23° C measured using the Dome Method y GOST MsanPiN 001-96 9.5.2 Physical Specifications Table 31.
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QSSC-S4R Technical Product Specification System Overview 9.6.2 Fans Eight fans are located at the upper front of the system for general cooling and are numbered system fan 1 through 8 if viewing the front of the system.
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System Overview QSSC-S4R Technical Product Specification 9.6.3 Hard Drive Slots The hard drive slots are numbered zero through seven starting from bottom right to left if viewing the front of the system. 9.6.4 PCIe Slots The PCIe slots are numbered one through ten starting from left to right if viewing the rear of the system. 9.6.5 Memory Riser Boards The memory riser slots are numbered one through eight as shown in the following image. 9.6.
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QSSC-S4R Technical Product Specification System Overview 9.6.7 NIC Ports The Quad-Gigabit Ethernet ports on the I/O riser board are numbered from 1 to 4, as shown below. 9.6.8 USB Ports The USB ports are numbered zero through two starting from top to bottom on the front panel, and three and four starting from top to bottom on the rear panel as shown below.
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System Overview QSSC-S4R Technical Product Specification 9.6.9 Power Supply Units The power bay provides space for four power supply modules and the power distribution board (PDB). The power supply is numbered 1 through 4 starting from right to left when viewing the rear of the system, as shown below.
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QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies 10. System Chassis and Sub-Assemblies 10.1 Base Chassis and Top Covers 10.1.1 Base Chassis The system is designed to fit into a standard 19-inch EIA rack and is 4U high x 28-inches deep. The 4U height is defined by standard EIA rack units where 1U = 1.75-inches. The depth, as measured from the front mounting flange to the back of the PCI slots, does not include cables.
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System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification Figure 33. Slide Rail Mounting Features Figure 34. Slide Rail mounted on the System Chassis with the Cable Management Arm attached at the back of the system 10.1.4 Cable Management Arm The server chassis is designed to accommodate Cable Management Arm (CMA) for sorting cables located at the back of the system. It is designed to be installed with the slide rails where there are inserting tabs for assembling.
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QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies Figure 36. Power Supply Unit (PSU) 10.2.1 Power Supply Modules The output rating of each power supply is 850 watts when operated between 200 VAC and 240 VAC. Modules are current-sharing and have auto-ranging input. Each power supply is 7.75 inches wide, 14.5 inches deep, and 1.47 inches high. The power supply modules have universal AC input with Power Factor Correction (PFC) Distributed Power Supplies (DPS).
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System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification Figure 37. Power Supply Indicators Note: The cooling system is non-redundant if only two power supplies are installed in the Value SKU. Caution Power supplies must be hot swapped within three minutes to prevent overheating. This time period applies only to the time that the power supply is physically removed, not from the time of failure. Table 35.
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QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies Figure 38. Fan Location Figure 39. S4R Fan Module In addition, there are two dual-motor fans located within each power supply drawing air through the hard drives and across the power distribution board. Note: The cooling system is non redundant in a non-redundant power supply system configuration. The zones are designed to be redundant in order to maintain system cooling in the event of fan failure.
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System Chassis and Sub-Assemblies 10.2.2.2 QSSC-S4R Technical Product Specification Fan Module Functional Block Diagram Figure 40. Fan Module Functional Block Diagram 10.2.2.3 Connector Signal Description and Pinouts The fan module sends fan signals via a 2x3 connector to the front panel fan board (FPFB) as shown in the below table. Table 36. Fan Module Connector Signal Description and Pinouts Pin 1 2 3 10.2.2.
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QSSC-S4R Technical Product Specification System Chassis and Sub-Assemblies Figure 41. Main Board Mount Structure & Strengthened CPU Heat-sink Figure 42.
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System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification x CPU heat-sink dividers isolate the flow channels through each CPU and eliminate the need for CPU dummies x Provided air deflectors for IOH and VR cooling CPU heat-sinks are board mounted, as shown in the figure below. Figure 43. Strengthened CPU installation on Main Board 10.4 Peripheral Bay Subsystem The following peripheral devices are supported: x Hard Disk Drives x Slim-line SATA DVD-RW drive x One 5.
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QSSC-S4R Technical Product Specification Caution System Chassis and Sub-Assemblies To ensure proper airflow and server cooling, all drive bays must contain either a carrier with a hard drive installed in it or a carrier with a HDD blank installed. The drive carriers contain light-pipes that allow LED indicators to display the hard drive status. Item Description A.
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System Chassis and Sub-Assemblies QSSC-S4R Technical Product Specification 10.4.3 5 ¼” Tape Drive Bay The system includes a bay that can support a half height 5.25” tape device. The system includes a 5.25” device blank for the 5.25” device opening. It matches the shape and interface of a 5.25” device. The blank includes the 5.25” device rails such that field upgrade to 5.25” device is possible. This is supported in the Enterprise SKU.
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QSSC-S4R Technical Product Specification Cables and Connectors 11. Cables and Connectors This section describes interconnections between the various components of the system. In addition, this section includes an overview diagram of the system interconnections and tables describing the signals and pin-outs for the user accessible connectors. 11.1 Interconnect Block Diagram Figure 48.
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Cables and Connectors QSSC-S4R Technical Product Specification 11.2 Cable and Interconnect Descriptions The following table describes all cables and connectors of QSSC-S4R. Table 38.
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QSSC-S4R Technical Product Specification Type SATA Quantity 5 AC Power DC Power From Main Board Cables and Connectors To HSBP Power supply Power supply External interface Power Distribution Board (PDB) Interconnect Description 29-pin SATA/SAS Drive Connector AC power cord Card Edge Gold Finger DC Power PSU Signal Fan Signal FP Signal DC Power DC Power DC Power HSBP Control System Fan Processors Memory 3 1 1 1 PDB PDB Main Board Main Board PDB PDB PDB FPFB Main Board Main Board FPFB FPFB HSBP FP
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Cables and Connectors QSSC-S4R Technical Product Specification Figure 49. COM Serial Port Connector 11.3.2 Video Ports The main board and front panel fan board (FPFB) provides respectively a video port interface with a standard VGAcompatible, 15-pin connector via IBMC. One located at the front – from the FPFB, and the other at the rear – from the main board. Table 41.
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QSSC-S4R Technical Product Specification Table 42. Dual USB Connector Pin-out (Rear) Pin 1 2 3 4 5 6 7 8 Signal Description Fused Voltage Controlled Current (VCC) (+5 V with over-current monitoring) USBPxN (differential data line) USBPxP (differential data line) GND (ground) Fused VCC (+5 V with over-current monitoring) USBPxN (differential data line) USBPxP (differential data line) GND (ground) Table 43.
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850W Power Supply QSSC-S4R Technical Product Specification 12. 850W Power Supply This section describes some of the QSSC-S4R Power Supply features. For a complete specification of the 850W high efficiency power supply, please see the QSSC-S4R 850W Power Supply Specification. The QSSC-S4R uses a 2+2/ or 3+1 redundant 850W high efficiency power supply. It has 2 outputs: 12V and 3.3Vsb. It is a current sharing power supply with auto ranging input and power factor corrected.
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QSSC-S4R Technical Product Specification A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 12VIBUS ILOCAL SCL SDA A0 A1 3.3VRS +3.3VSB +3.3VSB +3.3VSB VINGOOD ACRANGE PRESENT 850W Power Supply B6 B7 B8 B9 B10 B11 B12 P1 P2 P3 P4 P5 P6 PSALERT PSON +15VCC PSKILL +3.3VSB +3.3VSB +3.3VSB +12V RETURN +12V RETURN +12V +12V RETURN +12V +12V 12.3 AC Input Requirement AC input connector is an IEC 320 C-14 15A/250VAC power inlet. 12.3.
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850W Power Supply QSSC-S4R Technical Product Specification 12.3.6 Power Factor Correction (PFC) The power supply incorporates a Power Factor Correction circuit. The power factor is greater than 0.99 at 100VAC to 127VAC input voltages under 50% to 100% loading. 12.3.7 AC Input Connector The AC input receptacle is an IEC-320* C14 15A rated for 250VAC minimum. 12.
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QSSC-S4R Technical Product Specification 850W Power Supply 12.4.4 Short Circuit Protection A short circuit, which is defined as an impedance of 0.1 ohms or less, applied to any output during start-up or while running will not cause any damage to the power supply (connectors, components, PCB traces, etcetera). TBC When the +3.3VSB is shorted the output may go into “hiccup mode.” When the +3.3VSB attempts to restart, the maximum peak current from the output must be less than 8.0A.
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850W Power Supply QSSC-S4R Technical Product Specification 12.4.10 Power Supply Module LED indicators Figure 53. Power Supply Indicators Table 51. Power supply indicators LED A B C LED Name DC Power Redundancy status Power Supply Failures and Warnings AC Power Supply Input Status 12.4.10.
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QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 13. Power Distribution Board (PDB) This section describes the Quanta® Server System S4R power distribution board (PDB). 13.1 Introduction The QSSC-S4R power distribution board (PDB) is designed to plug directly to the output connectors of the power supply unit (PSU) and it contains the control logic supporting the cold redundancy feature, along with 240VA additional protection circuitry for one of the outputs and a FRU EEPROM.
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Power Distribution Board (PDB) QSSC-S4R Technical Product Specification Figure 55. Power Supply Numbering on the PDB The QSSC-S4R PDB supports the following features: x Board size: 15.35” (390mm) x 3.31” (84mm) x Tool-less attached x Four power supply card edge gold fingers – the power supply unit (PSU) hot docks to the PDB with mating connectors on the PSU side and gold fingers along the PDB edge, as shown in Figure 55. Power Supply Numbering on the PDB.
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QSSC-S4R Technical Product Specification Power Distribution Board (PDB) Figure 56. PDB Functional Block Diagram 13.2.1 Connector Signal Description and Pin-outs This section describes signal detail and pin definition of both the inlet card edge interface and output interface connectors. 13.2.1.1 Power Distribution Board Inlet Card Edge Interface Table 53.
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Power Distribution Board (PDB) QSSC-S4R Technical Product Specification Table 54. PDB Inlet Card Edge Interface – Component Side Pin B1 B2 B3 B4 B5 B6 B7 B8 13.2.1.2 Signal Description VINGOOD ACRANGE PRESENT CRMODE PWOK PSALERT PSON +15VCC Pin B9 B10 B11 B12 P4 P5 P6 Signal Description PSKILL +3.3VSB +3.3VSB +3.3VSB SGND +12V +12V Output Interface Connectors Table 55.
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QSSC-S4R Technical Product Specification 4 5 6 7 8 P12V P12V P12V P12V P12V Power Distribution Board (PDB) 12 13 14 15 16 GND GND GND GND P12V Vendor Molex Pin 9 10 11 12 13 14 15 16 P/N 39-30-6168 Signal Description P12V GND GND GND GND GND GND P12V Vendor Foxconn Pin 3 4 P/N HM3502E-P2 Signal Description GND GND Vendor Molex Pin 7 8 9 10 11 12 P/N 39-30-0120 Signal Description P3V3_STBY GND GND GND P12V_SENSE_RETURN P12V Table 57.
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Power Distribution Board (PDB) 7 9 11 13 15 17 19 21 23 25 27 29 31 33 QSSC-S4R Technical Product Specification SMB_LINK_3V3SB_CLK SMB_LINK_3V3SB_DAT PS1_PWRGOOD PS1_PRESENT_N PS2_VIN_GOOD PS3_PWRGOOD PS3_VIN_GOOD PS4_PWRGOOD PS4_PRESENT_N PS_INT_ALERT_N NC System Reserved* PS3_AC_RANGE NC 8 10 12 14 16 18 20 22 24 26 28 30 32 34 * PWOK_SYS = System POK GND GND PS1_VIN_GOOD PS2_PWRGOOD PS2_PRESENT_N GND PS3_PRESENT_N PS4_VIN_GOOD PS_FORCEPR_N PS_EN_R_N PWOK_SYS * System Reserved* PS4_AC_RANGE NC * PS
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QSSC-S4R Technical Product Specification Power Distribution Board (PDB) *Provided by droop share and the loading only under static not apply to start-up, AC-Off and hot- swap applications. 13.2.4 Dynamic Loading The output voltages shall remain within limits specified in table above for the step loading and capacitive loading specified in the table below. The load transient repetition rate shall be tested between 50Hz and 5 kHz at duty cycles ranging from 10%-90%.
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Power Distribution Board (PDB) 1. 2. 3. 4. 5. 6. 7. 8. QSSC-S4R Technical Product Specification PSAlert#_1 PSAlert#_2 PSAlert#_3 PSAlert#_4 PS1_OCP PS2_OCP PS3_OCP PS4_OCP 13.2.10 PMBus Requirements The PMBus features are limited to passing the I2C signals from the power supply modules to the system baseboard and vice versa. The FRU data format (FRU EEPROM located on PDB) is compliant with the IPMI specifications. 13.
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QSSC-S4R Technical Product Specification Power Distribution Board (PDB) 13.3.2 Cold Redundancy Functional Description The circuit always enables at least one power supply module once system PS_ON (PS_Enable) signal is generated. The number of enabled modules depends on the power consumed by the system and active modules status.
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Power Distribution Board (PDB) QSSC-S4R Technical Product Specification Figure 58. Power Sub-system Efficiency in Cold Redundant Operation The table below lists the PSs that would be enabled in different power ranges: Table 66.
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QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel 14. Front Panel Fan Board (FPFB) and Operator Panel The front panel contains the following: x Operator Panel with system control buttons and LED status indicators. For more information on the operator panels, refer to “Front Panel Control“ on page 123. x Four LED status indicators for the rear LAN ports x One video connector supporting 1280 x 1024 resolution x Three USB 2.0 ports 14.
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Front Panel Fan Board (FPFB) and Operator Panel QSSC-S4R Technical Product Specification 14.2 Front Panel Fan Board (FPFB) Functional Architecture 14.2.1 Front Panel Fan Board (FPFB) Connector Signal Description and Pinouts Item A B C D E F G Description 2X20 Pin Fan Signal 2X2 Pin Fan Power 1X8 Pin Hot Swap Back Plane Power 2X20 Pin Front Panel to Main Board 2X7 Pin USB to Main Board Fan Hot Swap Power Connectors 1-8 Front Panel LEDs and I/O Ports (see “page 123” for details Figure 59.
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QSSC-S4R Technical Product Specification Front Panel Fan Board (FPFB) and Operator Panel Table 67. System Fan Mapping System Fan 1 2 3 4 5 6 7 8 PWM 0 1 2 3 0 1 2 3 Tach 1 2 3 4 5 6 7 8 Fault 1 2 3 4 5 6 7 8 The tables below describe the signaling detail and pin-out information of the major connectors located on the FPFB. Table 68.
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Front Panel Fan Board (FPFB) and Operator Panel 1 2 3 4 5 6 7 8 QSSC-S4R Technical Product Specification SMB_IPMB_3V3SB_CLK GND SMB_IPMB_3V3SB_DAT RST_PWRGD_HSBP P3V3 FAN_PWRGD VR_PWROK P3V3_AUX Table 71. Hot-swap Fan Signal Description and Pinouts Pin 1 2 3 4 5 6 Description GND P12V FAN_TACHx FAN_PWMx FAN_PRSNTx_N LED_FANx_FAULT Table 72.
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QSSC-S4R Technical Product Specification 3 4 5 6 LED_ID_P SW_NMI_N SW_RST_N LED_STAT_P Front Panel Fan Board (FPFB) and Operator Panel 9 10 11 12 LED_STBY_P LED_MAIN_P SW_PWR_N GND Table 74. USB Header to Front Panel Signal Description and Pinouts Pin 1 2 3 4 5 6 7 Description Key Pin NC USB_FP_5V_PWR012 USB_ICH_P2N_FP USB_ICH_P2P_FP GND USB_FP_5V_PWR012 Pin 8 9 10 11 12 13 14 Description USB_ICH_P1N_FP USB_ICH_P1P_FP GND USB_FP_5V_PWR012 USB_ICH_P0N_FP USB_ICH_P0P_FP GND Table 75.
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Front Panel Fan Board (FPFB) and Operator Panel QSSC-S4R Technical Product Specification Figure 60. Operator Panel Controls and Indicators Table 77.
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QSSC-S4R Technical Product Specification G System reset button I System ID button J System power button K NMI button Front Panel Connectors H Video connector L Front Panel Fan Board (FPFB) and Operator Panel Resets the system Toggles ID LED Toggles system power Asserts NMI Three USB connectors Video port, standard VGA compatible, 15-pin connector (1280 x 1024 resolution support) Three USB 2.0 ports, 4-pin connectors 14.3.2 Functional Block Diagram 14.3.3 Connector Definition and Pinout Table 78.
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Basic Input/Output System (BIOS) QSSC-S4R Technical Product Specification 15. Basic Input/Output System (BIOS) 15.1 BIOS Architecture The BIOS is implemented as firmware that resides in the Flash ROM. It provides hardware-specific initialization algorithms and standard PC-compatible basic input/output (I/O) services, and standard QSSC-S4R Server Board features. The Flash ROM also contains firmware for certain embedded devices.
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QSSC-S4R Technical Product Specification BIOS Initialization 16. BIOS Initialization 16.1 Processors QSSC-S4R server boards are four socket boards that may have one, two, three or four processors installed. When a single processor is installed, it must be installed into CPU Socket 1. 16.1.1 CPUID Intel® Xeon® 7500 series processor and its next generation processor (Westmere-EX) are supported on QSSC-S4R.
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BIOS Initialization QSSC-S4R Technical Product Specification Table 79. CPU Population Rules for QSSC-S4R Number of CPUs CPU1 CPU2 CPU3 CPU4 9 X X X 1 9 9 X X 2 9 9 X X 2 9 9 9 X 3 9 9 9 9 4 1. In one CPU configuration, always populate CPU1 x 2. This will ensure that the primary CPU socket is always populated. In two CPU configuration, populate CPU1 and CPU3 x This ensures full I/O connectivity and hence maximum I/O availability x An alternate, reduced I/O 2-S population is also supported.
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QSSC-S4R Technical Product Specification BIOS Initialization code. The system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system. x Major: If the “Post Error Pause” setup option is enabled, the system goes directly to the Error Manager to display the error and log the error code to SEL. Otherwise, the system continues to boot and no prompt is given for the error, although the error code is logged to the Error Manager and in a SEL message.
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BIOS Initialization Error Population Rule Violation QSSC-S4R Technical Product Specification Severity x x x x System Action Logs the error in the SEL Does not disable any processors if possible. Displays “019C: Generic Processor Population Error” Continues to boot normally on to the OS. 16.1.11 Intel® Hyper-Threading Technology The QSSC-S4R BIOS detects processors that support Intel® Hyper-Threading Technology (Intel® HT Technology) and enables the feature during POST.
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QSSC-S4R Technical Product Specification BIOS Initialization 16.1.15 Enhanced Halt State (C1E) All processors support the Halt State (C1) through the native processor instructions HLT and MWAIT. Some processors implement an optimization of the C1 state called the Enhanced Halt State (C1E) to further reduce the total power consumption while in C1.
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BIOS Initialization QSSC-S4R Technical Product Specification x Turbo Boost operates under OS control – it is only entered when the OS requests the highest (P0) performance state. x Turbo Boost operation can be enabled or disabled by BIOS. x Turbo Boost converts any available power and thermal headroom into higher frequency on active cores. At nominal marked processor frequency, many applications consume less than the rated processor power draw.
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QSSC-S4R Technical Product Specification Bit[7:0] 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8F BIOS Initialization "LLC Array Error" "Tag Array Error" "State/Core valids Array Error" "LRU Array Error" "Protocol Error" "Tag multi-hit Error" "CAMD programming Error" "CAMD MCA Error" "COH/RSP TruthTable error" "MAF Timeout Error" "Multiple MAF entries PA matched" "Corrected PrefetchHint to non-coherent error" "Non-pipeline related Parity Error" Event Data 2 Bits[7:0] Reserved Event Da
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BIOS Initialization QSSC-S4R Technical Product Specification The BIOS configures the memory system dynamically in accordance with the available DDR-3 DIMM population and the selected RAS (Reliability, Availability and Serviceability) mode of operation. QSSC-S4R supports only RDIMMs. Figure 61. Memory Topology 16.2.1 Memory Sizing and Configuration The BIOS supports various memory module sizes and configurations. These combinations of sizes and configurations are valid only for DDR3 DIMMs.
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QSSC-S4R Technical Product Specification BIOS Initialization Any of the above errors also signal a memory error beep code. Memory beep code errors are described in Section 21.3.4. 16.2.3 Displaying System Memory x The BIOS displays the “Total Memory” of the system during POST if Quiet Boot is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.
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BIOS Initialization 16.2.4.1 QSSC-S4R Technical Product Specification Processor Cores, QPI Links and DDR3 Channels Frequency Configuration The Intel® Xeon® 7500 series processor connects to other Xeon® 7500 processors and to Intel® 7500 Chipset through Intel® Quick Path Interconnect (QPI) technology. The frequencies of the processor cores and the QPI links of Intel® Xeon® 7500 processor are independent from each other.
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QSSC-S4R Technical Product Specification BIOS Initialization Figure 62. QSSC-S4R System Memory Topology Figure 63. QSSC-S4R Memory DIMM Topology and DIMM Population Order 16.2.8 Memory Sub-System Nomenclature Intel® Xeon® 7500 processor has two Integrated Memory Controllers (IMCs). Each IMC has one Branch. Each Branch is routed to a memory board socket and consists of two SMI (Scalable Memory Interconnect) channels.
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BIOS Initialization x QSSC-S4R Technical Product Specification The optimization techniques like lock step are used by the Intel® Xeon® 7500 processor to maximize memory bandwidth. Some guidelines must be followed when populating DIMMs. Below are DIMM population guidelines. 1. Minimum one Memory board with minimum one DIMM pair of same type must be populated to boot the system. That is to say, pair DIMM 1/B and DIMM 1/D is minimum requirement to boot the system and system will be in lock step mode. 2.
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QSSC-S4R Technical Product Specification BIOS Initialization 27. If NUMA is enabled, BIOS can have only 2-way interleaving enabled or NO interleaving. Since 8-way, 4-way interleaving is not supported along with NUMA. 28. If Inter Socket mirroring is enabled, BIOS can have only 2-way interleaving or None. 29. Inter Socket mirroring will be disabled when NUMA is enabled. 30. Inter socket mirroring across IOH is not supported.
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BIOS Initialization QSSC-S4R Technical Product Specification Figure 65. Population with Non-identical DDR3 DIMMs x DIMMs within a Lock step pair must be of same organization. In the above configuration, DIMM 1/B & DIMM 1/D should be of the same organization. x However, DIMMs across lock step DIMM pairs need not be identical. For example, DIMM 1/B and DIMM 2/B can be of different type. x In the above configuration, DIMM sparing is not supported. Figure 66.
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QSSC-S4R Technical Product Specification BIOS Initialization Figure 67. Minimal Optimal Population Upgrade for RAS Modes x DIMM pairs {DIMM 1/B, DIMM 1/D}, {DIMM 1/A, DIMM 1/C} of Board 1 and 2 must be of same organization, size, and speed for Mirroring RAS. x The above population can be used to configure Mirroring, Sparing and Interleaving. Figure 68. Incorrect population for mirroring and sparing x DIMM 1/B and DIMM 1/D of Board 1 and 2 are identical in organization, size, and speed.
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BIOS Initialization QSSC-S4R Technical Product Specification Table 82.
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QSSC-S4R Technical Product Specification 16.2.10.1 BIOS Initialization Lock Step Mode. Lock step mode is where cache lines are divided across lock step SMI links. Minimum one DIMM pair of same type must be populated across the SMI channels to boot the system in lock step mode. Figure 69. Lock step mode Example BIOS will not provide any setup option to choose Lock Step Mode. BIOS will configure lock step mode by default and DIMMs that does not follow to lock step mode rules will be disabled.
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BIOS Initialization x QSSC-S4R Technical Product Specification Memory hot-plug can be supported in 2-way, 4-way or 8-way interleave mode but hot added memory will not be interleaved. BIOS setup will provide option for interleaving. When Memory RAS is set to Maximum Performance in setup, memory is always interleaved across IMCs of same Socket along with Hemisphere mode if memory configuration supports for better performance. 16.2.10.
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QSSC-S4R Technical Product Specification BIOS Initialization Figure 70. Intra-Socket Mirroring 16.2.10.4.2 Inter-Socket Mirroring Intel® Xeon® 7500 processor supports mirroring memory between two IMCs across CPU sockets. Inter Socket Mirroring Pairs depend upon the hemisphere mode. Inter Socket Mirroring pairs will change based on hemisphere type. One IMC is configured as primary and one IMC is configured as secondary in each CPU socket when Hemisphere mode is None.
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BIOS Initialization QSSC-S4R Technical Product Specification MEM1_SLOT MEM2_SLOT MEM3_SLOT MEM4_SLOT CPU1 CPU2 CPU3 CPU4 CPU1 MEM5_SLOT MEM6_SLOT MEM7_SLOT MEM8_SLOT Note: The arrow points from Primary to Secondary Copy of Memory Data Figure 71. Inter-Socket Mirroring 16.2.10.
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QSSC-S4R Technical Product Specification BIOS Initialization Figure 72. Hemisphere Example 16.2.10.5.1 NUMA in Hemisphere Mode Hemisphere mode is enabled by default if system memory configuration supports. When NUMA is enabled in BIOS Setup Inter-Socket interleaving will be disabled because when NUMA is enabled only 2-way interleaving is supported.4-way or 8-way interleaving is not possible along with NUMA. NUMA can be enabled even if Hemisphere mode is disabled. 16.2.10.5.
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BIOS Initialization QSSC-S4R Technical Product Specification MEM1_SLOT MEM2_SLOT MEM3_SLOT MEM4_SLOT CPU1 CPU2 CPU3 CPU4 CPU1 MEM5_SLOT MEM6_SLOT MEM7_SLOT MEM8_SLOT Note: The arrow points from Primary to Secondary Copy of Memory Data Figure 73. Mirroring in Hemisphere Mode 16.2.11 Memory Hot-Plug Memory Hot-plug is the ability to upgrade the system memory at runtime while the operating system is running, without the need for bringing down the system.
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QSSC-S4R Technical Product Specification 16.2.11.1 BIOS Initialization Detailed Flow The following flow illustrates the overall process of memory hot-add on QSSC-S4R: User Domain Begin Power LED Off User inserts memory riser board in an empty riser slot Attention button BIOS will log SEL to indicate error. OS Domain User presses attention button OS then invokes ASL code to trigger hotadd. If this step fails OS Notification (SCI) The BIOS then sets the Power LED solid on.
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BIOS Initialization QSSC-S4R Technical Product Specification The following flow illustrates the overall process of hot-removal of memory board on QSSC-S4R. Figure 75. Memory Hot-Remove Flow Based on the above flows, a hot-replace operation involves the following operations: 1. Memory mirroring is enabled.
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QSSC-S4R Technical Product Specification BIOS Initialization NUMA has to be enabled for any memory hot plug operations. Population rules for Memory Hot Add and Hot Replace are described as follows: 16.2.11.3.1 Memory Hot Add in Hemisphere mode x BIOS recommend to hot add two risers when System is in Hemisphere mode. x If user hot adds only one riser. BIOS will log memory configuration error. x When the user adds two risers, both risers must be inserted.
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BIOS Initialization 16.2.11.3.10 QSSC-S4R Technical Product Specification Memory Hot Replace in Inter Socket Mirroring Mode Memory Hot Replace not supported in Inter Socket Mirroring Mode. If user tries to hot replace memory in Inter Socket Mirroring mode, BIOS will log a configuration error SEL. 16.2.12 Memory Error Handling This section describes the BIOS and chipset policies used for handling and reporting errors occurring in the memory subsystem.
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QSSC-S4R Technical Product Specification 16.2.12.1.3 BIOS Initialization Faulty Data Paths DDR-3 DIMM technology includes data paths from the DIMMs to the memory controller. Therefore, errors or failures can occur on the serial path between DDR-3 DIMMs. These errors are different from ECC errors, and do not necessarily occur as a result of faulty DRAM cells.
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BIOS Initialization QSSC-S4R Technical Product Specification BIOS Error Manager Screen The BIOS reports RAS configuration errors where the installed DDR3 DIMMs are disabled because of population errors. Beep Codes The BIOS emits a beep code for cases where the system has no memory, or when a fatal error like Memory BIST error is detected during memory discovery, BIOS Setup Screen RAS configuration errors are captured in the Advanced | Memory screen in the BIOS setup.
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QSSC-S4R Technical Product Specification 16.2.12.2.1.1 BIOS Initialization Device Location Information The QSSC-S4R system defines memory devices in units of CPU sockets, Memory Boards, Intel® SMI Link, DDR3 Channel and finally DIMM slots. This information is available in the SMBIOS tables as Type 16 and Type 17 records.
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BIOS Initialization QSSC-S4R Technical Product Specification CPU4 MEM7_SLOT MEM8_SLOT Table 87. Formats of Memory RAS State SEL Record for Memory Mirroring 5GPUQT 5GPUQT 6[RG %QFG 'XGPV 4GCFKPI 0x0C 6[RG %QFG 0x0B 0WODGT 0x01 'XGPV &CVC 0xA0 0xA1 &GUETKRVKQP Memory RAS State Information for Memory Mirroring Memory is configured in the Mirrored mode, and the memory is operating in the fully redundant state.
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QSSC-S4R Technical Product Specification BIOS Initialization Event Data 2 Bits [3:0] Sparing Type When ED2[7:4] = 0000b (Local Sparing Domain) 0000b – Reserved 0001b – DIMM Sparing 0010b – Rank Sparing 0011b - 1110b: Reserved When ED2[7:4] = 0001b (Global Sparing Domain) 1111b - This field is unused and does not contain valid data. Note: DIMM Sparing and Ranking sparing cannot co-exist.
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BIOS Initialization QSSC-S4R Technical Product Specification Table 90. Formats of Memory RAS Configuration SEL Record for Memory Sparing Sensor Number Sensor Type Code Event/Reading Type Code 0x13 0x0C 0x09 Description Memory RAS Configuration Information for Memory Sparing Event Data 1 0x01 Memory Spare RAS Configuration Mode has been activated. 0x00 Memory Spare RAS Configuration Mode has been disabled Event Data 2 Always 00h Event Data 3 Always 00h 16.2.12.2.
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QSSC-S4R Technical Product Specification 16.2.12.2.2.2 BIOS Initialization Memory Mismatch and Configuration Errors Table 92. Format of Memory Mismatch Error SEL Records Sensor Number 0x03 Event Data 1 0xA7 Event Data 2 Bits [5] Bits [4] Bits [3:0] Event Data 3 Bits[7:4] Bits[3] Bits [2:0] 16.2.12.2.2.
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BIOS Initialization 16.2.12.2.2.4 QSSC-S4R Technical Product Specification Patrol Scrub Error Records Table 95. Format of Patrol Scrub Error SEL Records Sensor Number 0x0B Event Data 1 0xA0 0xA1 Event Data 2 Bits [7:0] Event Data 3 Bits[7:4] Bits[3] Bits [2:0] Sensor Type Code 0x0C Event/Reading Type 0x76 Description Patrol Scrub Error Correctable Error Uncorrectable Error Reserved. Set to 0. Index of Memory Board experiencing the Scrub ECC error. Reserved.
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QSSC-S4R Technical Product Specification 16.2.12.2.3 BIOS Initialization Memory BIST Error Reporting There are a number of conditions that can be detected and reported during Memory BIST, which includes the initialization of the memory subsystem. During memory discovery, any DDR3 DIMMs that cannot be initialized or ones that fail Memory BIST are disabled. 1.
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BIOS Initialization 9. QSSC-S4R Technical Product Specification If any DIMM has been marked as disabled for “MemBIST Failure” (does not include “SPD Failure” or “Population Error), assuming the there are still usable DIMMs available in the system: x The BIOS sounds a memory error beep code. x Error Manager Major error codes 0xE6xx (Memory BIST Failed) and 0xE1xx (DIMM disabled) are displayed and logged to SEL for each DIMM that failed and was disabled. x The System Status LED is set to AMBER/ON. 10.
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QSSC-S4R Technical Product Specification 16.2.12.2.6 BIOS Initialization DIMM Fault Indicator LEDs Intel® Boxboro-EX Chipset server boards that use the Intel® Nehalem-EX processor have a fault-indicator LED adjacent to each DIMM socket on the memory boards. The LEDs are turned on when the DDR-3 DIMM on the adjacent DIMM socket generates the error events described below. The generic usage model for the DIMM Fault LEDs is described in the following table. Table 98.
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BIOS Initialization QSSC-S4R Technical Product Specification The SMI essentially intercepts the MCE, and the BIOS SMI handler reads the Platform Configuration Space Registers (PCSR) to determine the error that occurred, and for memory errors to identify the DIMM that was the source of the error. The BIOS SMI handler reports the error by logging it to the SEL, and performs any other required actions.
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QSSC-S4R Technical Product Specification BIOS Initialization ® Generates POST Diagnostic code 0xEB and generates Memory Error Beep code No SEL records generated No DIMM fault LEDs lit No Status LED code No SMBIOS record No Error Manager error codes System is halted ® Generates error beep code Uncorrected ECC error for each bad DIMM Fault LEDs are LIT for all failed DIMM s Amber/O n SMBIOS Type 131 maps out DIMMs that have been disabled. Type 17 shows empty sockets.
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BIOS Initialization QSSC-S4R Technical Product Specification 166
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QSSC-S4R Technical Product Specification BIOS Initialization Table 102. Memory ECC Error Handling — Runtime, Non-Redundant Configuration Error Scenario Correctable Errors System Event DIMM Fault System Log (SEL) LED Fault LED None No change No change IPMI Memory RAS System Behavior Operation None The system continues to operate normally.
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BIOS Initialization QSSC-S4R Technical Product Specification Table 103.
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QSSC-S4R Technical Product Specification BIOS Initialization may vary from boot to boot with varying presence of PCI devices with PCI-PCI bridges. If a bridge device with a single bus behind it is inserted into a PCI bus, all subsequent PCI bus numbers below the current bus are increased by one. The bus assignments occur once, early in the BIOS boot process, and never change during the pre-boot phase. 16.3.
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BIOS Initialization QSSC-S4R Technical Product Specification 16.6.1 Native USB Support During the power-on self test (POST), the BIOS initializes and configures the USB subsystem in accordance with Chapter 14 of the Extensible Firmware Interface Reference Specification, Version 1.1.
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QSSC-S4R Technical Product Specification BIOS Initialization User Domain OS Domain OS Domain Begin OS HP driver searches for and loads device driver for the hot-plugged device.
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BIOS Initialization 5 6 7 8 9 IOH-2 IOH-2 IOH-2 IOH-2 IOH-2 10 11 ICH-10 IOH-1 Gen2 x8 8Gbps Gen2 x8 8Gbps Gen2 x8 8Gbps Gen2 x4 4Gbps Gen1 (ESI) x4 2Gbps Gen1 x4 2Gbps Gen2 x8 8Gbps 12 13 IOH-1 ICH-10 PCIe/ESI x4 2Gbps Gen1 x1 512Mbps 14 15 IOH-1 IOH-1 Gen1 x2 1Gbps Gen1 x2 1Gbps QSSC-S4R Technical Product Specification PCI Express x8 Slot 5 PCI Express x8 Slot 6 PCI Express x8 Slot 7 PCI Express x8 Slot 8 PCI Express x4 Slot 9 PCI Express x8 Slot 10 PCI Express x8 Slot for SAS riser ESI (IOH-to
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QSSC-S4R Technical Product Specification BIOS Initialization x Get Fan Configuration: Used to get the SDR records from the BMC. If no profiles are supported, the BMC defaults to profile 0. x Set Fan Configuration: Used by the BIOS to x x Enable a supported BMC Fan Control profile x Communicate to the BMC that the BIOS has completed the setup of the memory throttling and DIM temperature sensor state. x Provide DIMM temperature sensor availability data to the BMC.
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BIOS Initialization Byte 3 QSSC-S4R Technical Product Specification Name 4 Record Subtype Flags 5 Profile Support Bitmap 6:N Thermal Profile Data Thermal Profile Data Record Description Value 0Bh [7:2] – Reserved [1:0] – Memory throttling mode that this record is valid for 0 = None supported 1 = Open-loop throughput throttling (OLTT) 2 = Close-loop thermal throttling (CLTT) 3 = reserved [7:0] Fan Control Profile Support.
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QSSC-S4R Technical Product Specification 16.9.1.4 BIOS Initialization Closed Loop Thermal Throttling (CLTT) QSSC-S4R support Fan Speed Control (FSC) in Closed Loop Thermal Throttling (CLTT) fashion. OLTT is NOT supported. CLTT is enabled by default by BIOS. Also in QSSC-S4R only RDIMM are supported. If RDIMM with a failed Thermal Sensor is detected CLTT will not be enabled and BIOS error manager will show that error.
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BIOS User Interface QSSC-S4R Technical Product Specification 17. BIOS User Interface 17.1 Splash Logo / Diagnostic Screen The Logo / Diagnostic Screen appear in one of two forms: x If Quiet Boot is enabled in the BIOS setup, a logo splash screen is displayed. By default, Quiet Boot is enabled in the BIOS setup. If the logo is displayed during POST, press to hide the logo and display the diagnostic screen.
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QSSC-S4R Technical Product Specification BIOS User Interface Table 108. Memory Thermal Throttling OEM SDR bytes 6:N details Functional Area Title Bar Description The title bar is located at the top of the screen and displays the title of the form (page) the user is currently viewing. It may also display navigational information. Setup Item List The Setup Item List is a set of controllable and informational items. Each item in the list occupies the left column of the screen.
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BIOS User Interface QSSC-S4R Technical Product Specification + Change Value The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboards, but will have the same effect.
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QSSC-S4R Technical Product Specification 17.2.3.1 BIOS User Interface Main Screen The Main screen is the first screen that appears when the BIOS Setup is entered, unless an error has occurred. If an error has occurred, the Error Manager screen appears instead. Main Advanced Security Server Management Logged in as: Platform ID Boot Options Boot Manager System BIOS Version QSSC-S4ROCI.xx.yy.
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BIOS User Interface Setup Item Quiet Boot Options Enabled Disabled QSSC-S4R Technical Product Specification Help Text [Enabled] – Display the logo screen during POST. Comments [Disabled] – Display the diagnostic screen during POST. POST Error Pause Enabled Disabled [Enabled] – Go to the Error Manager for critical POST errors. [Disabled] – Attempt to boot and do not go to the Error Manager for critical POST errors.
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QSSC-S4R Technical Product Specification 17.2.3.2 BIOS User Interface Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, you can select the option to be configured. Configurations are performed on the selected screen, and not directly on the Advanced screen. To access this screen from the Main screen, press the right arrow until the Advanced screen is selected.
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BIOS User Interface 17.2.3.3 QSSC-S4R Technical Product Specification Processor Configuration Screen The Processor configuration screen allows you to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor.
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QSSC-S4R Technical Product Specification BIOS User Interface Table 112. Setup Utility — Processor Configuration Screen Fields Setup Item Options (Default in Boldface) Processor ID Processor Frequency Core Frequency Microcode Revision L1 Cache RAM L2 Cache RAM L3 Cache RAM CPU Status Processor 1 Version Processor 2 Version Processor 3 Version Processor 4 Version ® Current Intel QPI Link Speed ® Intel QPI Link Frequency Intel(R) QPI Frequency Auto Max Select 4.8 GT/s 5.866 GT/s 6.
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BIOS User Interface QSSC-S4R Technical Product Specification Setup Item Options Help Text Comments (Default in Boldface) Technology for Directed Enabled ® Directed I/O(Intel VT-d). I/O Report the I/O device assignment to VMM through DMAR ACPI Tables Interrupt Remapping Disabled ® ® Enable/Disable Intel VT-d Interrupt Remapping This option only appears when Intel Enabled support. Virtualization Technology for Directed I/O is enabled.
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QSSC-S4R Technical Product Specification BIOS User Interface 17.2.3.3.1 Memory Configuration Screen The Memory configuration screen allows you to view details about the system memory DDR3 DIMMs that are installed. This screen also allows you to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, select Advanced > Memory.
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BIOS User Interface Setup Item QSSC-S4R Technical Product Specification Options (Default in Boldface) Speed Memory RAS and Performance Configuration Help Text Comments running at. Select to configure the memory RAS and Configure memory RAS performance. This takes the user to a different (Reliability, Availability, and Serviceability) and view current screen. memory performance information and settings. 17.2.3.3.
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QSSC-S4R Technical Product Specification Sparing Mode DIMM Sparing Rank Sparing NUMA Optimized Disabled Enabled Memory Interleaving none 2 Way 4 Way 8 Way Enabled Disabled Auto 512G 1024G 64G 128G Disabled Enabled Memory Hot Plug Memory Hot Plug Base Memory Hot Plug Length SRAT Memory Hot Plug BIOS User Interface [Intra-Socket Mirroring] - IMC is mirrored with the other IMC in the same socket.
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BIOS User Interface Setup Item QSSC-S4R Technical Product Specification Options Help Text Comments Spare Unit: The DDR3 DIMM is functioning as a spare unit for memory RAS purposes. Note: X denotes the Board identifier . 17.2.3.3.4 Mass Storage Controller Configuration Screen The Mass Storage configuration screen allows you to configure the SATA/SAS controller when it is present on the baseboard, midplane or backplane of an Intel system.
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QSSC-S4R Technical Product Specification BIOS User Interface 17.2.3.3.5 Serial Port Configuration Screen The Serial Ports Configuration screen allows you to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port. Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Figure 84.
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BIOS User Interface QSSC-S4R Technical Product Specification 17.2.3.3.6 USB Configuration Screen The USB Configuration screen allows you to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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QSSC-S4R Technical Product Specification Enabled Disabled USB 2.0 controller BIOS User Interface On-board USB ports are enabled to support USB 2.0 mode. Contact your OS vendor regarding OS support of this feature. devices can be displayed here. This field is grayed out if the USB Controller is disabled. 17.2.3.3.7 PCI Configuration Screen The PCI Configuration Screen allows you to configure the PCI add-in cards, onboard NIC controllers, and video options.
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BIOS User Interface QSSC-S4R Technical Product Specification Setup Item Options Onboard NIC3 ROM Enabled Disabled Onboard NIC4 ROM Enabled Disabled Onboard NIC iSCSI ROM Enabled Disabled NIC 1 MAC Address No entry allowed NIC 2 MAC Address No entry allowed NIC 3 MAC Address No entry allowed NIC 4 MAC Address No entry allowed Intel ® I/OAT Enabled Disabled Help Text Comments Warning: If [Disabled] is selected, NIC2 cannot be used to boot or wake the system.
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QSSC-S4R Technical Product Specification 17.2.3.4 BIOS User Interface Security Screen The Security screen allows you to enable and set the user and administrative password. This is done to lock out the front panel buttons so they cannot be used. This screen also allows the user to enable and activate the Trusted Platform Module (TPM) security settings. To access this screen from the Main screen, select Security.
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BIOS User Interface Setup Item TPM Administrative Control QSSC-S4R Technical Product Specification Options No Operation Turn On Turn Off Clear Ownership Help Text Comments is in the same state as a disabled TPM except setting of the TPM ownership is allowed if not present already. An enabled and activated TPM executes all commands that use the TPM functions and TPM security operations are also available. [No Operation] - No changes to current state. [Turn On] - Enables and activates TPM.
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QSSC-S4R Technical Product Specification 17.2.3.5 BIOS User Interface Server Management Screen The Server Management screen allows you to configure several server management features. This screen also provides an access point to the screens for configuring console redirection and displaying system information. To access this screen from the Main screen, select Server Management.
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BIOS User Interface Setup Item Detection QSSC-S4R Technical Product Specification Options Disabled Console Redirection Help Text play loading of an IPMI driver. Do not enable if your OS does not support this driver. View/Configure console redirection information and settings. System Information View system information BMC LAN Configuration View/Configure BMC LAN channel and User settings. Comments Takes the user to the Console Redirection screen. Takes the user to the System Information screen.
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QSSC-S4R Technical Product Specification BIOS User Interface To access this screen from the Main screen, select Server Management > System Information. Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 91. Setup Utility — Server Management System Information Screen Table 124.
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BIOS User Interface QSSC-S4R Technical Product Specification Server Management BMC Configuration Baseboard LAN configuration IP Source IP Address Subnet Mask Gateway IP Static/ Dynamic Intel ® RMM3 LAN configuration Intel ® RMM3 IP Source IP Address Subnet Mask Gateway IP Static/ Dynamic BMC DHCP Host Name User Configuration User ID Privilege User status User Name User Password. anonymous/root/User3/User4/User5 Callback/ User/ Operator/ Administrator Disable/ Enable Figure 92.
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QSSC-S4R Technical Product Specification Setup Item IP source BIOS User Interface Options Static Dynamic Help Text IP address View / Edit IP address. Press to edit. Subnet Mask View / Edit subnet address. Press to edit. Gateway Mask View / Edit Gateway IP address. Press to edit. Intel® RMM3 Information only. Display whether RMM3 present/ Not present BMC Host Name View / Edit BMC host name. Press to edit.
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BIOS User Interface QSSC-S4R Technical Product Specification Boot Option #1 Boot Option #2 Boot Option #x Hard Disk Order CDROM Order Network Device Order BEV Device Order Add New Boot Option Delete Boot Option EFI Optimized Boot Enabled / Disabled Use Legacy Video for EFI OS Enabled / Disabled Boot Option Retry Enabled / Disabled USB Boot Priority Enabled / Disabled Figure 93.
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QSSC-S4R Technical Product Specification Disabled USB Boot Priority Enabled Disabled based boot options without waiting for user input. If enabled, newly discovered USB devices are moved to the top of their boot device category. If disabled, newly discovered USB devices are moved to the bottom of their boot device category. BIOS User Interface This option enables or disables the “USB Reorder” functionality. For more information, see Section 19.1.2.
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BIOS User Interface QSSC-S4R Technical Product Specification 17.2.3.8.1 Add New Boot Option Screen The Add Boot Option screen allows you to add an EFI boot option from the boot order. To access this screen from the Main screen, select Boot Options > Add New Boot Option. Boot Options Add New Boot Option Add boot option label Select Filesystem Path for boot option Save Figure 94. Setup Utility — Add New Boot Option Screen Display Table 127.
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QSSC-S4R Technical Product Specification BIOS User Interface 17.2.3.8.3 Hard Disk Order Screen The Hard Disk Order screen allows you to control the hard disks. To access this screen from the Main screen, select Boot Options > Hard Disk Order. Boot Options Hard Disk #1 < Available Hard Disks > Hard Disk #2 < Available Hard Disks > Figure 96. Setup Utility — Hard Disk Order Screen Display Table 129.
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BIOS User Interface QSSC-S4R Technical Product Specification Table 131. Setup Utility — CDROM Order Fields Setup Item Floppy Disk #1 Floppy Disk #2 Options Available Legacy devices for this device group. Available Legacy devices for this device group. Help Text Set the system boot order by selecting a boot option for this position. Set the system boot order by selecting a boot option for this position. Comments 17.2.3.8.
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QSSC-S4R Technical Product Specification BIOS User Interface Table 133. Setup Utility — BEV Device Order Fields Setup Item BEV Device #1 Options Available Legacy devices for this device group. Help Text Set the system boot order by selecting a boot option for this position. BEV Device #2 Available Legacy devices for this device group. Set the system boot order by selecting a boot option for this position. 17.2.3.
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BIOS User Interface 17.2.3.11 QSSC-S4R Technical Product Specification Exit Screen The Exit screen allows you to choose whether to save or discard the configuration changes made on the other screens. It also allows you to restore the server to the factory defaults or to save or restore them to a set of user-defined default values. If Load Default Values is selected, the factory default settings (noted in bold in the tables in this chapter) are applied.
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QSSC-S4R Technical Product Specification BIOS User Interface 17.3 Loading BIOS Defaults Different mechanisms exist for resetting the system configuration to the default values. When a request to reset the system configuration is detected, the BIOS loads the default system configuration values during the next POST. The request to reset the system to the defaults can be sent in the following ways: x Pressing from within the BIOS Setup utility. x Moving the clear system configuration jumper.
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BIOS Update Support QSSC-S4R Technical Product Specification 18. BIOS Update Support 18.1 BIOS Update and Recovery One Boot Flash Update refers to the ability to update the BIOS while the server is online and operating. If an update to the system BIOS is not successful or if the system fails to complete POST and the BIOS is unable to boot an OS, it may be necessary to run the BIOS recovery procedure.
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QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 19. Operating System Boot, Sleep, and Wake 19.1 Boot Device Selection The Boot Device Selection phase is responsible for controlling the booting of the system. The boot option variables are set by an OS during OS installation or manually added by the user through the Boot Maintenance Manager of the Setup utility. The Boot Maintenance Manager provides the capability to make permanent changes to the boot order.
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Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 19.1.3 Boot Order Table The BIOS supports the Boot Order Table (BOT), which exposes the system boot order along with device priority orders. In addition, the Boot Order table includes the device names and hardware path details in addition to the boot priority order. The Boot Order Table is located in IPMI System boot options OEM parameter 125.
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QSSC-S4R Technical Product Specification Tables 0 The system Boot Order. 1 Order of devices within first device class. Operating System Boot, Sleep, and Wake … N Order of devices within last device class. Terminator Note that while the Terminator must be last, the other tables can occur in any order. The BIOS is required to include Order Tables for the Boot Order and for each class that has a device. The management application need not include all Order Tables.
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Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification 19.1.3.3.1 Non-EFI Order Tables A legacy or OEM device order is 2+n bytes, where n is the number of devices in the order. The Terminator order follows the same format with n=0. Table 140. BOT Non-EFI Order Tables Offset Name Length 0h Order type 1 Byte 01h 02h Order Length Device Order List 1 Byte Order Length BYTEs Order Table (for non- EFI devices) Description This field specifies the type of order.
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QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 19.1.3.3.2 EFI Device Order Table EFI device orders are similar, but the elements in the Device Order List are WORDs rather than BYTEs (2 + 2n bytes, where n is the number of EFI devices in the order): Table 141. BOT EFI Device Order Table Offset Order Table Length Order type 1 Byte 01h 02h Order Length Device order list 1 Byte Order Length WORDs (for nonEFI devices) 19.1.3.
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Operating System Boot, Sleep, and Wake 19.1.3.5 QSSC-S4R Technical Product Specification 05h Name Varies Null-terminated Unicode string. The string is UTF-16 encoding format as specified in Unicode 1.2 standard. Varies Device path Path Length EFI Device path of a particular device Obtaining the Boot Order Table The BIOS checks the BOT for updates (see Section 19.1.3.6) during POST, prepares a new BOT describing the current boot order, and then stores the BOT in OEM parameter 125.
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QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake The BIOS supports ACPI 3.0, 2.0 and 1.0b tables. To prevent conflicts with a non-ACPI-aware OS, the memory used for the ACPI tables is marked as “reserved” in INT 15h, function E820h. As described in the ACPI specifications, an ACPI-aware OS generates an SMI to request that the system be switched into the ACPI mode.
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Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification The wake-up sources are enabled by the ACPI operating systems with cooperation from the drivers; the BIOS has no direct control over the wake-up sources when an ACPI OS is loaded. The role of the BIOS is limited to describing the wake-up sources to the OS and controlling secondary control / status bits via the Differentiated System Description Table (DSDT). The S5 state is equivalent to the OS shutdown.
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QSSC-S4R Technical Product Specification 19.2.3.2 Operating System Boot, Sleep, and Wake WHEA Software Stack The Operating System (OS) kernel is responsible for installing the Platform-Specific Hardware Error Drivers (PSHED) and providing them with the necessary services. While the PSHED is channeled towards the BIOS for hardware error flow management, the OS Kernel also exposes the interfaces and API (WheaReportHwErr) to user-level applications called “HW error event consumer”.
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Operating System Boot, Sleep, and Wake QSSC-S4R Technical Product Specification Note: SATA SW RAID and EFI Optimized Boot are mutually exclusive options. SATA SWRAID can boot only in Legacy Boot mode. For more information on the two options in the BIOS setup, see Section 17.2.3.3. and Section 17.2.3.3.4. 19.2.5 Intel® Turbo Boost Technology Based on Intel® Xeon® 7500 series processor, QSSC-S4R supports the Intel® Turbo Boost Technology feature.
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QSSC-S4R Technical Product Specification Operating System Boot, Sleep, and Wake 19.4.2 Wake Events / SCI Sources The server board supports the following wake-up sources in the ACPI environment. The OS controls the enabling and disabling of these wake-up sources: x Devices that are connected to any USB port, such as USB mice and keyboards, can wake the system from the S1 sleep state. x The serial port can be configured to wake the system from the S1 sleep state.
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BIOS Role in Server Management QSSC-S4R Technical Product Specification 20. BIOS Role in Server Management The BIOS supports many standard-based server management features and several proprietary features. The Intelligent Platform Management Interface (IPMI) is an industry standard and defines standardized, abstracted interfaces to platform management hardware.
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QSSC-S4R Technical Product Specification BIOS Role in Server Management x followed by a two-second pause must be interpreted as a single escape. x followed within two seconds by one or more characters that do not form a sequence described in this specification must be interpreted as plus the character or characters, not as an escape sequence. The escape sequence in the following table is an input sequence. This means it is sent to the BIOS from the remote terminal. Table 147.
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BIOS Role in Server Management QSSC-S4R Technical Product Specification features and then take control of the system reset or power using the Channel Mode features. If a failure occurs during POST, a watchdog time-out feature in the BMC automatically takes control of the COM2 port. The character sequence that switches the multiplexer to the BMC serial port is “ESC O 9” (denoted as ^[O9). This key sequence is above the normal ANSI function keys and is not used by an ANSI terminal. 20.3.
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QSSC-S4R Technical Product Specification BIOS Role in Server Management 20.5 System Management BIOS (SMBIOS) The BIOS provides support for the System Management BIOS Reference Specification, Version 2.5, to create a standardized interface for manageable attributes that are expected to be supported by DMI-enabled computer systems. The BIOS provides this interface via data structures through which the system attributes are reported.
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BIOS Role in Server Management QSSC-S4R Technical Product Specification The structure types listed with a table have specific data that is filled in every BIOS. The Structure types without a table either follow the SMBIOS specification for filling in its fields or have fields that are dynamically filled according to the heading of the structure type. 20.5.2.
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QSSC-S4R Technical Product Specification 06h Version Byte String 07h Serial Number Byte String 08h UUID 16 bytes Varies 18h Byte Enum 19h Wakeup Type Interrupt Info SKU Number Byte String 1Ah Family Byte String 20.5.2.3 BIOS Role in Server Management Number of the Null-terminated string. This comes from the FRU field “Product Version”. Number of the Null-terminated string. This comes from the FRU field “Product Serial Number”.
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BIOS Role in Server Management Offset 19h Name Length Value 1Ah Processor Byte Upgrade L1 Cache Handle Word Offset 1Ch Name Length Value L2 Cache Handle Word Varies 1Eh L3 Cache Handle Word Varies 20h Serial Number Byte String 21h 22h Asset Tag Part Number Byte Byte String String 23h Core Count Byte Varies 24h Core Enabled Byte Varies 25h Thread Count Byte Varies 26h Processor Characteristics Word Bit Field 20.5.2.
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QSSC-S4R Technical Product Specification Offset Name 05h Cache Configuration Length Value Byte Varies 07h Maximum Cache Size Word Varies 09h Installed Size Word Varies 0Bh Supported SRAM Word Type Current SRAM Word Type Cache Speed Word Error Correction Byte Type System Cache Byte Type Associativity Byte 0Dh 0Fh 10h 11h 12h 20.5.2.
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BIOS Role in Server Management 04h Count 20.5.2.11 Byte 05 QSSC-S4R Technical Product Specification Number of strings. Type 12 Structure — System Configuration Options The SMBIOS Type 12 structure contains strings describing the configuration settings of all jumpers and switches on the server board. 20.5.2.12 Type 13 Structure — BIOS Language Information The SMBIOS Type 13 structure contains the number of installed languages and the currently configured language for the BIOS. Table 154.
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QSSC-S4R Technical Product Specification Offset 08h Name Handle Total Width Word Varies Total width, in bits, of this memory device, including any check or ECC bits. If no error-correction bit is present, total width = data width.
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BIOS Role in Server Management 20.5.2.19 QSSC-S4R Technical Product Specification Type 38 Structure — IPMI Device Information The SMBIOS Type 38 structure describes the attributes of the embedded IPMI controller on the server board. In addition to the SMBIOS 2.3.1 Specification, two bytes have been appended to the Type 38 structure to provide information about the interrupt used by the embedded IPMI controller and about the IPMI base address. Table 157.
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QSSC-S4R Technical Product Specification BIOS Role in Server Management 20.6 Security 20.6.1 BIOS Setup Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. Both User and Administrator passwords are supported by the BIOS. An Administrator password must be entered in order to set the User password.
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BIOS Role in Server Management QSSC-S4R Technical Product Specification x Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled OS to verify system boot integrity. x Produces EFI and legacy interfaces to a TPM enabled OS for utilizing TPM. x Produces ACPI TPM device and methods to allow a TPM enabled OS to send TPM administrative command requests to the BIOS. x Verifies operator physical presence. Confirms and executes OS TPM administrative command requests.
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QSSC-S4R Technical Product Specification BIOS Error Handling 21. BIOS Error Handling 21.1 Fault Resilient Booting Fault Resilient Booting (FRB) is an Intel-specific feature that detects and handles errors during the system boot process. The FRB feature guarantees the system boots without hanging. Failures during the booting process that can be detected and handled by the BIOS and BMC include: x BSP POST Failure (FRB-2) x OS load failures 21.1.
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BIOS Error Handling QSSC-S4R Technical Product Specification is displayed in the Error Manager if “POST Error Pause” is enabled. In any case, the Error Code 0x8198 is logged to the SEL. For details on the format of the events logged, see Section 21.2.3.6. 21.1.3 Operating System Watchdog Failure In addition, the Operating System or OS drivers or the Server Management Software (SMS) may use the BMC Watchdog Timer to prevent a permanent hang in the OS.
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QSSC-S4R Technical Product Specification x BIOS Error Handling Errors and warnings detected during POST, and logged as POST errors – these are discussed separately in Section 21.2.2 Finally, there is one class of errors that may have been partially handled by BIOS in previous generations of Intel® Server Boards, but no longer are: x MA Sensors – these are now handled exclusively by the Operating System drivers and error-handling mechanisms.
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BIOS Error Handling QSSC-S4R Technical Product Specification 21.2.3.1.1 Fatal/Uncorrectable Errors Table 159.
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QSSC-S4R Technical Product Specification Sensor Name Critical Interrupt SensorED1 specific Offset OEM09h 7:6=10b specified 5:4=10b 13h 70h Critical Interrupt OEM0Ah specified 13h 70h PCIe Fatal Received 04h ERR_FATAL message from downstream Error ('PCIe Fat Sensor‘) Critical Interrupt OEM0Bh specified 13h 70h PCIe Fatal Unexpected Completion Error ('PCIe Fat Sensor') Critical Interrupt OEM0Ch specified 13h 70h Critical Interrupt OEM0Dh specified 13h 70h PCIe Fatal ACS Violation Error
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BIOS Error Handling Sensor Name QSSC-S4R Technical Product Specification Sensor Number Cor Sensor‘) Sensor Type 13h Sensor Name Sensor Number Sensor Type PCIe Correctable Advisory 05h non-fatal Error (received ERR_COR message) ('PCIe Cor Sensor‘) Critical Interrupt 13h PCIe Correctable Link 05h bandwidth changed (ECN) Error ('PCIe Cor Sensor‘) Critical Interrupt 13h E/R Type Sensorspecific Offset ED1 ED2 ED3 71h E/R Type Sensorspecific Offset OEM05h specified 71h 3:0= 04h: Replay Timer tim
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QSSC-S4R Technical Product Specification BIOS Error Handling Address Parity errors are errors detected in the memory addressing hardware. Since these affect the addressing of memory contents, they can potentially lead to the same sort of failures as ECC errors. They are logged as a distinct type of error since they affect memory addressing rather than memory contents, but otherwise they are treated exactly the same as Uncorrectable ECC Errors.
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BIOS Error Handling QSSC-S4R Technical Product Specification Sensor Name Sensor Number Sensor Type E/R Type Sensorspecific Offset ED1 ED2 ED3 17h – to provide additional Offset values.) 21.2.3.5 Compute Module Extension Sensors See the EPSD Blade Extension External Product Specification, Revision 1.0 for additional sensors that may be reported by some Compute Module models. 21.2.3.
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QSSC-S4R Technical Product Specification BIOS Error Handling The BMC logs this event in the SEL, and the system restarts and goes through POST. There are two differences between this case and the “OS Load timer” case – first, the Timer Purpose in the BMC SEL Event is different, and secondly, there is no POST Error Code generated by BIOS during the reboot.
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BIOS Error Handling Event Data 2 0 = ID is IPMB slave address As a result, the generator ID byte will go up in increments of 2 for events logged by System Software Generator IDs. See the Intelligent Platform Management Interface Specification, Version 2.0. Number of sensor that generated this event. 6Fh if event offsets are specific to the sensor. 7:6 00b = unspecified byte 2 10b = OEM code in byte 2 5:4 00b = unspecified byte 3 10b = OEM code in byte 3.
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QSSC-S4R Technical Product Specification Progress Code 0x28 BIOS Error Handling Progress Code Definition Testing memory PCI Bus 0x50 Enumerating PCIe buses 0x51 Allocating resources to PCIe buses 0x52 Hot-plug PCIe controller initialization 0x53-0x57 Reserved for PCIe Bus USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA / ATAPI / SATA Progress Code 0x5A Progress Code Definition Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserve
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BIOS Error Handling Progress Code QSSC-S4R Technical Product Specification Progress Code Definition 0xE0 Started dispatching early initialization modules (PEIM) 0xE2 Initial memory found, configured, and installed correctly 0xE1, 0xE3 Reserved for initialization module use (PEIM) Driver eXecution Environment (DXE) Core (not accompanied by a beep code) 0xE4 Entered EFI driver execution phase (DXE) 0xE5 Started dispatching drivers 0xE6 Started connecting drivers DXE Drivers (not accompanied by
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QSSC-S4R Technical Product Specification BIOS Error Handling Note: for 0048 “Password check failed”, the system halts, and then after the next reset/reboot will displays the error code on the Error Manager screen. x Fatal: The system halts during post at a blank screen with the text “Unrecoverable fatal error found. System will not boot until the error is resolved” and “Press to enter setup” The POST Error Pause option setting in the BIOS setup does not have any effect with this class of error.
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BIOS Error Handling QSSC-S4R Technical Product Specification Error Code 0x84F3 Baseboard Management Controller in Update Mode. Major 0x84F4 Baseboard Management Controller Sensor Data Record empty. Major 0x84FF Baseboard Management Controller System Event Log full. Minor 0x8604 Chipset Reclaim of non critical variables complete. Minor 0xA000 TPM device not detected. Major 0xA001 TPM device is missing or not responding. Major 0xA002 TPM device failure.
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QSSC-S4R Technical Product Specification BIOS Error Handling Table 170. POST Error Beep Codes Beeps 3 Error Message Memory error POST Progress Code Description multiple System halted when a fatal error related to the memory was detected and system does not have available memory. 3 Memory Test Error 0xEB The system generates a Memory Error beep code and then continues to boot if System has available memory.
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Baseboard Management Controller (BMC) QSSC-S4R Technical Product Specification 22. Baseboard Management Controller (BMC) 22.1 Feature Support 22.1.1 IPMI 2.0 Features x Baseboard management controller (BMC). x IPMI Watchdog timer. x Messaging support, including command bridging and user/session support. x Chassis device functionality, including power/reset control and BIOS boot flags support. x Event receiver device: The BMC receives and processes events from other platform subsystems.
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QSSC-S4R Technical Product Specification Baseboard Management Controller (BMC) x Front panel management: The BMC controls the system status LED and chassis ID LED. It supports secure lockout of certain front panel functionality and monitors button presses. The chassis ID LED is turned on using a front panel button or a command. x Power state retention. x Power fault analysis. x Intel® Light-Guided Diagnostics. x Power unit management: Support for power unit sensor.
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Baseboard Management Controller (BMC) x QSSC-S4R Technical Product Specification 250 MHz 32-bit ARM9 Processor x Memory Management Unit (MMU) x Two 10/100 Ethernet Controllers with NC-SI support x 16 bit DDR2 667 MHz interface x Dedicated RTC x 12 10-bit ADCs x Eight Fan Tachometers x Four PWMs x Battery-backed Chassis Intrusion I/O Register x JTAG Master x Six I2C interfaces x General-purpose I/O Ports (16 direct, 64 serial) x Additionally, ServerEngines* Pilot II integrates a su
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QSSC-S4R Technical Product Specification BMC Functional Specifications 23. BMC Functional Specifications 23.1 Power System The BMC is in-line with the system power control path. This is implemented by an integrated hardware signal passthrough. The pass-through allows the BMC to directly block power-on if necessary. If the BMC firmware is nonfunctional, the default state of the pass-through hardware is to allow full system control.
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BMC Functional Specifications QSSC-S4R Technical Product Specification must also coincide with the assertion of the “CPU Power Failure Status” bit in the chipset. Note that BIOS must deassert the “CPU Power Failure Status” bit on a normal power-on. If the BMC detects a power-good dropout, the following occurs: 1. Hardware powers down the system. 2. The BMC asserts the Power Unit Failure offset of the Power Unit sensor and logs a SEL event. See Section 24.25.1.4. 3.
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QSSC-S4R Technical Product Specification 23.1.5.1 BMC Functional Specifications Power Button Signal The POWER_BUTTON signal is filtered through a 16 ms hardware debounce. The signal must be in a constant state for more than 16 ms before it is treated as asserted. The signal is routed to the chipset power button signal through passthrough and SIO circuitry that allows the BMC to lock out the signal.
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BMC Functional Specifications QSSC-S4R Technical Product Specification x The watchdog timer is stopped. x The power, reset, front panel NMI, and ID buttons are unprotected. x Fan speed control is determined by available SDRs. Fans may be set to a fixed state, or basic fan management can be applied. The BMC detects that the system has exited the ACPI S1 sleep state when it is notified by the BIOS SMI handler. S2 No Not supported S3 No Not supported S4 No Not supported S5 Yes Soft off.
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QSSC-S4R Technical Product Specification BMC reset IPMI command BMC Functional Specifications No Yes 23.3.3 Front Panel System Reset The reset button is a momentary contact button on the front panel. Its signal is routed through the front panel connector to the BMC, which monitors and de-bounces it. The signal must be stable for at least 16 ms before a state change is recognized. If the reset button is locked by the BMC, then the button will not reset the system. 23.3.
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BMC Functional Specifications QSSC-S4R Technical Product Specification After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads the watchdog timer with the new timeout interval. If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so configured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes. The BMC then hard resets the system, assuming the BIOS selected reset as the watchdog timeout action.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 24. Processor Presence and Population Check 24.1.1 BSP Identification The BMC cannot indicate which processor is the BSP. Software that needs to identify the BSP should use the multiprocessor specification tables. See the BIOS EPS. 24.1.2 Boot Control Support The BMC supports the IPMI 2.0 boot control feature that allows the boot device and boot parameters to be managed remotely.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification When AC power is first applied to the system, the status LED will turn solid amber, to indicate that the BMC is booting. If, upon completing the boot, the BMC does not detect abnormal conditions, the LED will turn off until the system is commanded-on. The LED state information below is dependent on the underlying sensor support. Table 174.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 24.2.3 Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced. The state of the chassis ID LED is affected by the following actions: x Toggled by turning the chassis ID button on or off. x Controlled by the IPMI Chassis Identify command. x Chassis Identify command can be used to blink or deactivate the Chassis ID LED. It cannot be used to set the LED in the solid-on state.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification 24.2.5 Secure Mode and Front Panel Lock-out Operation The front panel can be locked using the Set Front Panel Enables command. You can check the front panel lock-out status using the Get chassis Status command. 24.3 Private Management I2C Buses The BMC controls multiple private I2C buses. The BMC is the sole master on these buses.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 24.5 BMC Internal Timestamp Clock The BMC maintains a four-byte internal timestamp clock. The timestamp value is derived from an RTC element that is internal to the BMC. This internal timestamp clock is read and set using the Get SEL Time and Set SEL Time commands, respectively. The Get SDR Time command can also be used to read the timestamp clock.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification regardless of the system power state The BMC allocates 65,519 bytes of non-volatile storage space for the SDR. See Table 44 for SDR command support. 24.7.1 SDR Repository Erasure SDR repository erasure is a background process.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 06 1 A0h Memory Riser Board E RW 256 07 1 A2h Memory Riser Board F RW 256 08 1 A4h Memory Riser Board G RW 256 09 1 A6h Memory Riser Board H RW 256 0A 4 AAh Power Distribution Board RW 256 0B 4 A0h Power Supply 1 RO 256 0C 4 A2h Power Supply 2 RO 256 0D 4 A4h Power Supply 3 RO 256 0E 4 A6h Power Supply 4 RO 256 0F 5 AEh Front Panel Fan Board RW 256 10 5 A8h SAS (O
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Processor Presence and Population Check QSSC-S4R Technical Product Specification Table 178. NMI Signal Generation and Event Logging Causal Event NMI (IA IA-32 Only) Signal Generation Front Panel Diag Interrupt Sensor Event Logging Support Chassis Control command (pulse diagnostic interrupt) X – Front panel diagnostic interrupt button pressed X X Watchdog Timer pre-timeout expiration with NMI / diagnostic interrupt action X – 24.10 Sensor Rearm Behavior 24.10.1 Manual vs.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check Table 179.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification Upon BMC initialization, the processor presence offset is initialized to the deasserted state. The BMC then checks to see if the processor is present, setting the offset accordingly. This state is updated at each DC power-on and at system resets. If a processor is removed while the system has AC power, and the system is then powered-on (DC-on), the appropriate deassertion event will be logged (if enabled).
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QSSC-S4R Technical Product Specification Processor Presence and Population Check The BMC provides 10-bit A/Ds for voltage monitoring. The BMC FW reads this 10- bit value and scales it to fit into the 1-byte data field supported by IPMI. The BMC knows what scale factor to use by retrieving it from an OEM SDR which provides a scale factor for each voltage sensor in the system.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification the fan speed sensors and clears fan failure conditions. If the failure condition is still present, the boost state returns once the sensor has reinitialized and the threshold violation is detected again. 24.13.2 Fan Redundancy Detection The BMC supports redundant fan monitoring and implements a fan redundancy sensor.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check Such oscillation can be prevented by specifying positive or negative hysteresis, or both. Each time the fan speed contribution is calculated, the BMC uses the hysteresis values to create a window around the temperature value that was used for the calculation. The fan speed and the hysteresis window remain unchanged until a new sensor reading falls outside of the window.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification the table lookup is saved for reference. When the final domain contribution is calculated, it is reduced, if necessary, to this domain maximum value. This limits the maximum noise output of the system for a given ambient temperature to ensure acoustic specifications are met. Hysteresis is not applied to domain maximum sub-records. 24.13.4.
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QSSC-S4R Technical Product Specification 24.13.4.3 Processor Presence and Population Check Sensor Failure Each Tcontrol SDR sub-record has a failure control value field. The value in this field is used by the BMC as that subrecord’s fan speed contribution if the associated sensor is enabled but is marked reading/state unavailable. If the sensor is unreadable because it is disabled, or if a failure control value of FFh is specified, then the BMC ignores the sub-record’s fan speed contribution. 24.13.
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Processor Presence and Population Check 24.13.5.2 QSSC-S4R Technical Product Specification ASHRAE Compliance System requirements for ASHRAE compliance is defined in the Common Fan Speed Control & Thermal Management Platform Architecture Specification. Altitude-related changes in fan speed control are handled through profiles for different altitude ranges. 24.14 DIMM Thermal Margin Sensor QSSC-S4R platform supports system memory DIMMs with temperature sensing capabilities.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check In order for the BMC to handle these values in its fan speed control algorithms, any Tcontrol SDRs referencing these sensors must have the signed sensor flag bit set. The clamp temperature in the SDR is interpreted as a two’scomplement signed integer. 24.15 IOH thermal Margin Sensor QSSC-S4R platform supports two IOH, and each IOH supports on-die thermal sensor.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification AND x Processor VR current trip point (default setting: 90% of supported TDP current) is triggered. AND x System power utilization is high and exceeds a pre-set limit of 80% BMC monitors throttling of CPU and Memory Controller and logs an SEL event. Power throttle sensor is implemented as auto rearm sensor. Upon assertion of the sensor offset, BMC starts an internal time of 30 mins.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check x During runtime, if BIOS needs to return bus ownership to the BMC, it must first try to do this using the IPMI OEM command method. Only if the BMC doesn’t respond to the IPMI OEM command, then BIOS must reset the associated semaphore bit to indicate that the BMC now owns the bus. x During runtime, if BIOS needs to return bus ownership to the BMC, it must first try to do this using the IPMI OEM command method.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification Figure 109. BMC/BIOS interactions for Memory Hot-Plug/On-line/Off-line Operations 24.21 HeartBeat LED QSSC-S4R platform has a heartbeat LED located on top of IO riser (next to IO Riser power LED) which indicates BMC firmware health, it can be seen only if the chassis is open. On normal operating condition Heartbeat LED be green blinking with 1 sec of blink rate.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 3. Exit firmware transfer mode (BMC reset) will cause LED to stop blinking till firmware is up and running. 4. No other sensors any fault or system status would cause any impact to Heartbeat LED. 24.22 CSS LED QSSC-S4R has the CSS LED on back of IO Riser, which indicates Memory and Power Supply status. CSS LED supports only two states OFF and SOLID YELLOW.
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Processor Presence and Population Check Power Supply 2 B2h Power Supply 3 B4h Power Supply 4 B6h QSSC-S4R Technical Product Specification 24.24.2 PMBus -specific Sensor Support The following sensor types are supported for systems that contain PMBus-compliant power supplies and a PMBuscompliant power distribution board. 24.24.2.1 Power Supply Input Power Sensor This analog sensor monitors AC power input to the system.
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QSSC-S4R Technical Product Specification 05h 06h Processor Presence and Population Check power is applied to the system and the previous system power state was on. Soft power control failure – Asserted if the system fails to power-on due to the following power control sources: x Chassis Control command x PEF action x BMC Watchdog Timer x Power State Retention Power unit failure – Asserted for the following conditions: x Unexpected deassertion of system POWER_GOOD signal.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification Power supply fan sensors are implemented as manual re-arm sensors because a failure condition can result in boosting of the fans. This in turn may cause a failing fan’s speed to rise above the “fault” threshold and can result in fan oscillations. As a result, these sensors do not auto-rearm when the fault condition goes away but rather are rearmed only when the system is reset or power-cycled.
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QSSC-S4R Technical Product Specification Processor Presence and Population Check 70 80 90 100% 80% 80% 100 100% 80% 80% 4. HSC Temp: Apart from system Fan contribution, PS Fan would boost when BP temperature crosses threshold mentioned in clamp record. As BMC needs to poll HSC BP sensor continuously, new sensor 0xF0 has been added and the same is clamped for Domain 4 which is same as HSC BP temp sensor 0x01.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification 24.25.6 Power Unit Redundancy The BMC supports redundant power sub-systems and implements a Power Unit Redundancy sensor per platform. A Power Unit Redundancy sensor is of sensor type Power Unit (09h) and reading type Availability Status (0Bh).
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QSSC-S4R Technical Product Specification Processor Presence and Population Check Table 188 shows outputs that can be tested via the Set SM Signal command. Table 189. Set SM Signal Command Signal Definition Signal Name Fan power/speed Signal ID 05h Instances Note 1 System Fault LED (amber) 01h Note 1 System Ready LED (green) 0Fh Note 1 Notes For “force assert” actions, request byte 4 is required. For all other actions, request byte 4 is reserved, and should not be sent with the request.
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Processor Presence and Population Check QSSC-S4R Technical Product Specification DIMM DIMM Map for CPU Group 0, Riser 1 CPU Group 1, Riser 3 CPU Group 2, Riser 5 CPU Group 3, Riser 7 DIMM Location on riser DIMM_1B XXXXXXXX – XXXXXXXX – 00000000 – 00000001 D1/B DIMM_1D DIMM_1A DIMM_1C DIMM_2B DIMM_2D DIMM_2A XXXXXXXX – XXXXXXXX – 00000000 – 00000010 XXXXXXXX – XXXXXXXX – 00000000 – 00000100 XXXXXXXX – XXXXXXXX – 00000000 – 00001000 XXXXXXXX – XXXXXXXX – 00000000 – 00010000 XXXXXXXX – XXXXXXXX – 0000
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QSSC-S4R Technical Product Specification Processor Presence and Population Check All processors in a system have their CATERR pins tied together. The pin is used as a communication path to signal a catastrophic system event to all CPUs. The BMC has direct access to this aggregate CATERR signal. The BMC only monitors for the “CATERR held low” condition. A pulsed low condition is ignored by the BMC. If a CATERR-low condition is detected, the BMC logs an error message to the SEL against the CATERR sensor.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification 25.
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QSSC-S4R Technical Product Specification 1. User names for User IDs 1 and 2 cannot be changed. These will always be ““ (Null/blank) and “root” respectively. x 2. BMC Messaging Interfaces A “CCh” error completion code will be returned if a user attempts to modify these names. User 2 (“root”) will always have the administrator privilege level. x A “CCh” error completion code will be returned if a user attempts to modify this value.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification But, (per channel session limit) (bullet 4) > (total session slots) (bullet 3); this is done so that the available slots can be used optimally. Even then, the user might not be able to open the Maximum # sessions per channel on a particular channel. The Maximum per channel session limit is used only to maintain fairness in session usage across the Channels.
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QSSC-S4R Technical Product Specification BMC Messaging Interfaces 25.6.2 Receive Message Queue The receive message queue is only accessible via the SMS interface since that interface is the BMC’s host / system interface. The queue is two entries in size. Per- channel queue slots are not provided. 25.6.3 SMS / SMM Status Register Bits in the status register provide interface and protocol state information. As an extension to the IPMI 2.
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BMC Messaging Interfaces x An event is in the event message buffer x Watchdog pre-timeout interrupt flag has been set QSSC-S4R Technical Product Specification All conditions must be cleared and all BMC to SMS messages must be flushed for the SMS_ATN bit to be cleared. The host I/O address of the SMS interface is 0CA2h – 0CA3h. The operation of the SMS interface is described in the Intelligent Platform Management Interface Specification.
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QSSC-S4R Technical Product Specification BMC Messaging Interfaces 25.7.2 IPMB LUN Routing The BMC can receive either request or response IPMB messages. The treatment of these messages depends on the destination logical unit number (LUN) in the IPMB message. For IPMB request messages, the destination LUN is the responder’s LUN. For IPMB response messages, the destination LUN is the requester’s LUN. The disposition of these messages is described in Table 197.BMC IPMB LUN Routing.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification Figure 110. BMC IPMB Message Reception 25.8 IPMI Serial Feature The IPMI 2.0 Intel implementation of IPMI-over-serial was known as the emergency management port (EMP) interface before IPMI 1.0. The EMP nomenclature is no longer used. The BMC only supports terminal mode – direct connect on the serial interface.
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QSSC-S4R Technical Product Specification BMC Messaging Interfaces 25.8.2.2.2 Hex-ASCII Commands The BMC supports the IPMI binary commands specified in this document. The BMC supports the privilege level scheme for terminal mode text commands. 25.8.2.3 Bridging The BMC supports the optional bridging functionality described in the Intelligent Platform Management Interface Specification Second Generation v2.0. 25.8.2.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification IPMI 2.0 messaging introduces payload types and payload IDs to allow data types other than IPMI commands to be transferred. IPMI 2.0 serial-over-LAN is implemented as a payload type. Table 199. Supported RMCP+ Payload Types Payload Type 00h 01h 02h 10h – 15h Feature IPMI message Serial-over-LAN OEM explicit Session setup IANA N/A N/A Intel (343) N/A 25.9.
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QSSC-S4R Technical Product Specification BMC Messaging Interfaces 25.9.5.1.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification x When Block Size < 16, it must be the last Block request in this series. In other words Byte 2 is equal to “Update is complete” (1) on that request. x When ever Block Size < 16, the Block data bytes must end with a NULL Character or Byte (=0). x All Block write requests are updated into a local Memory byte array. When Byte 2 is set to “Update is Complete”, the Local Memory is committed to the NV Storage.
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QSSC-S4R Technical Product Specification BMC Messaging Interfaces 25.9.12 Platform Event Filter (PEF) The BMC includes the ability to generate a selectable action, such as a system power-off or reset, when a match occurs to one of a configurable set of events. This capability is called Platform Event Filtering, or PEF. One of the available PEF actions is to trigger the BMC to send a LAN alert to one or more destinations. The BMC supports 20 PEF filters.
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BMC Messaging Interfaces QSSC-S4R Technical Product Specification provides a text string that describes a simple description of the event. SMTP alerting is configured using the embedded web server.
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QSSC-S4R Technical Product Specification BMC Flash Update 26. BMC Flash Update 26.1 Logical Firmware Image Blocks The BMC firmware is divided into four main functional blocks: x Boot Block: Small firmware image containing a bootloader and cursory hardware initialization. It allows redownload of the operational code if it somehow becomes corrupted. x Operational Code: The main runtime firmware. This includes the embedded Linux kernel, and all applications.
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BMC Flash Update QSSC-S4R Technical Product Specification Firmware Transfer commands allow any area of the BMC flash to be updated. These functions understand the sector structure of the flash device used on the server board, so the update utility cannot issue sector erase commands. Instead flash sectors are implicitly erased as necessary before the first write to a sector.
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QSSC-S4R Technical Product Specification BMC Flash Update The jumper is normally in the de-asserted position. The system must be completely powered off (A/C power removed) before the jumper is moved. After power is re-applied and the firmware update is complete, the system must be powered off again and the jumper returned to the de-asserted position before normal operation can begin. There is no boot block write protection jumper. 26.
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BIOS-BMC Interactions QSSC-S4R Technical Product Specification 27. BIOS-BMC Interactions BIOS-BMC interactions include the following: x FRB2 Operation. x POST Complete Signaling – BIOS asserts the POST Complete signal at the end of POST. BMC firmware monitors this signal. x Retrieval of Platform Information – BIOS may query firmware revisions for the BMC and attached satellite controllers. BIOS may also read FRU device locator records from the BMC, to determine the system’s inventory.
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QSSC-S4R Technical Product Specification BMC-HSC Interactions 28. BMC-HSC Interactions 28.1 HSC Availability QSSC-S4R supports Hot-Swap Controller (HSC), the HSC is not available when the system is in standby. The HSC requires at least three seconds after DC-power-on to reach a working state where it will respond to IPMI commands. The state of the HSC is not preserved across system reset or AC/DC cycle. When a single HSC is present in a system, it will respond on the primary IPMB at address C0h.
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Sensors QSSC-S4R Technical Product Specification 29. Sensors Specific server boards may only implement a sub-set of sensors and / or may include additional sensors. The systemspecific details of supported sensors and events are described in the EPS for the specific server board or system. The actual sensor name associated with a sensor number may vary between server boards or systems. 29.
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QSSC-S4R Technical Product Specification Sensors Default Hysteresis x The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative hysteresis). Criticality x Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the front panel status LED. Standby x 305 Some sensors operate on standby power.
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Voltage 02h Voltage 02h 03h 04h 05h 06h 07h 08h 10h 15h 16h IPMI Watchdog (IPMI Watchdog) Physical Security (Physical Scrty) FP Interrupt (FP NMI Diag Int) SMI Timeout (SMI Timeout) System Event Log (System Event Log) System Event (System Event) BB +1.1V IOH (BB +1.1V IOH) BB +1.8V AUX (BB +1.8V AUX) BB +3.3V (BB +3.3V) BB +3.3V STBY (BB +3.3V STBY) BB +12.0V (BB +12.0V) BB +1.1V VIO Proc1/2 (BB +1.
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Temperature 01h Temperature 01h Temperature 01h Temperature 01h Temperature 01h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Fan 04h 22h 27h 2Ah 2Bh 2Ch 2Dh 2Eh 30h 32h 33h 34h 35h 36h 37h System Fan 3 (SYS Fan 3) System Fan 4 (SYS Fan 4) System Fan 5 (SYS Fan 5) System Fan 6 (SYS Fan 6) System Fan 7 (SYS Fan 7) System Fan 8 (SYS 307 31h 28h 26h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Fan 04h Temperature 01h 21h 25h Temperature 01h Voltage 02h Thre
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45h 46h 47h 48h 50h Fan 6 Present Sensor (Fan 6 Present) Fan Redundancy (Fan Redundancy) Fan 7 Present Sensors (Fan 7 Present) Fan 8 Present Sensors (Fan 8 Present) Power Supply 1 Status (PS1 Status) 52h Power Supply 08h 44h Fan 5 Present Sensor (Fan 5 Present) Power Supply 1 AC Fan 04h 43h Fan 4 Present Sensors (Fan 4 Present) 51h Fan 04h 42h Fan 3 Present Sensors (Fan 3 Present) Power Supply 2 Status (PS2 Status) Fan 04h 41h Fan 2 Present Sensor.
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Fatal OK [u] [c,nc] [u] [c,nc] [u] [c,nc] [u] [c,nc] 01 - Thermal trip 07 - Presence Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Current 03h Temperature 01h Temperature 01h Temperature 01h Temperature 01h Processor 07h Processor 07h Temperature 01h Temperature 01h Temperature 01h 55h 56h 57h 5Eh 5Fh 60h 61h 64h 65h 66h Processor 2 Status (P2 Status) Processor 1 Thermal Control % (P1 Therm Ctrl %) Processor 2 Thermal Control % (P2 Therm Ctrl %) Processor 1 VRD
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Threshold 01h Threshold 01h Threshold 01h Threshold 01h Temperature 01h Temperature 01h Power Supply 08h Power Supply 08h Other Units 0Bh Other Units 0Bh Current 03h Current 03h 76h 77h 80h 81h 82h 83h 84h 85h Processor 4 VRD Temp (P4 VRD Hot) Power Supply 3 Status (PS3 Status) Power Supply 4 Status (PS4 Status) Power Supply 3 AC Power Input (PS3 Power In) Power Supply 4 AC Power Input (PS4 Power In) Power Supply 3 +12V % of Maximum Current Output (PS3 Curr Out %) Power Supply 4 +12V % of M
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Curr Out %) Power Supply 1 Fan 14 (PS1 Fan X, X=1,2,3,4) Power Supply 2 Fan 14 (PS2 Fan X, X=1,2,3,4) Power Supply 3 Fan 14 (PS3 Fan X, X=1,2,3,4) Power Supply 4 Fan 14 (PS4 Fan X, X=1,2,3,4) DIMM Aggregate Temperature 1_2 ( DIMM Agg Tmp 1_2) DIMM Aggregate Temperature 3_4( DIMM Agg Tmp 3_4) DIMM Aggregate Temperature 5_6( DIMM Agg Tmp 5_6) DIMM Aggregate Temperature 7_8( DIMM Agg Tmp 7_8) Memory Buffer Aggregate Temperature 1_2 ( Mem Buf Tmp 1_2 ) Memory Buffer Aggregate Temperature 3_4 ( Mem Buf Tmp
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Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h Voltage 02h D2h D3h D4h D5h D6h D7h D8h OEM Sensor F3h C0h D1h Voltage 02h B7h Voltage 02h Voltage 02h B6h D0h Voltage 02h B5h BB VCORE CPU1 (BB VCORE CPU1) BB VCORE CPU2 (BB VCORE CPU2) BB VCACHE CPU1 (BB VCACHE CPU1) BB VCACHE CPU2 (BB VCACHE CPU2) BB +3.3V AUX (BB +3.
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QSSC-S4R Technical Product Specification Hot-Swap Controller (HSC) Architecture 30. Hot-Swap Controller (HSC) Architecture The HSC uses a VSC410* SAF-TE enclosure processor (SEP). This microcontroller employs a v3000 RISC CPU, 8 KB of internal SRAM, GPIO, SGPIO, two general purpose UARTs, one SPI, and four I2C compatible interfaces. Figure 111. HSC Interface Routing * If present, SGPIO is disconnected. ** If present, I2C3 is disconnected. 30.1.
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HSC Functional Specifications QSSC-S4R Technical Product Specification 31. HSC Functional Specifications 31.1 Platform Determination The HSC provides a unique platform identifier through several management interfaces. The table below shows the identifiers returned by the interfaces on the backplane. The I2C identification is returned as part of the IPMI Get Device ID response. The SAFTE and SES responses are part of the inquiry data.
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QSSC-S4R Technical Product Specification HSC Functional Specifications Table 206. Cable Detect Configuration Cable A Detected Cable B Detected Configuration No No Invalid Configuration: will use 8 disks by default. No Yes Invalid configuration: will use 8 disks by default. Yes No Will use 4 disks. Yes Yes Will use 8 disks. 31.3 System Event Log (SEL) The VSC410 controller does not implement a system event log. Instead, SEL entries are maintained by the BMC.
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HSC Functional Specifications QSSC-S4R Technical Product Specification 31.7 Disk Management 31.7.1 Drive Fault Light Control The HSC activates and deactivates drive fault LEDs according to the states received via SAFTE or SES pages, or the SGPIO bus. Only the host bus adapter can change the state of a disk. IPMI commands can be used to toggle the drive fault LEDs for diagnostic purposes. The HSC does not have control of the green drive ready / activity LEDs. Disk hardware controls these LEDs. 31.7.
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QSSC-S4R Technical Product Specification HSC IPMB Application and Sensors 32. HSC IPMB Application and Sensors This section presents the additional specifications required for the HSC’s implementation as an IPMI controller. See the Intelligent Platform Management Interface Specification for more information. 32.1 LUNs The HSC accepts Intelligent Platform Management Bus requests directed to its LUN 00.
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HSC IPMB Application and Sensors Drive Slot 5 Presence Drive Slot 6 Presence Drive Slot 7 Presence 0Fh QSSC-S4R Technical Product Specification Drive Slot (0Dh) Drive Slot (0Dh) Drive Slot (0Dh) 10h 11h 08h Presence auto dev. remove, dev. Inserted 08h Presence auto dev. remove, dev. Inserted 08h Presence auto dev. remove, dev. Inserted Notes: 1. Event messages are not generated for this sensor. 2. Only available when HSC is in eight-disk mode. 32.2.
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QSSC-S4R Technical Product Specification HSC Firmware Update 33. HSC Firmware Update The HSC firmware is stored in a separate SPI-compatible EEPROM module. This EEPROM is only accessible by the HSC to read or write operational code. The HSC reads code actively from the SPI EEPROM, which can contribute to increased execution times. 33.1 HSC Update Over IPMB Firmware updates primarily take place via the IPMB. This method requires a firmware update utility and an Intel hexformat image.
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HSC Firmware Update QSSC-S4R Technical Product Specification Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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QSSC-S4R Technical Product Specification LAN LED LPC LVDS MRH-D MTBF NIC OEM OLTP OS OTP OVP PAL PCI PDB PEF PEP PFC PIROM PLD PSU PVC PWM RAID RAS RH RPM SAF-TE SCA SCL SAS SDA SDINT SDR SDRAM SE SEEPROM SEL SIOH SMB SMP SNC-M SSI TTL USB UV VAC VCC VCCI VGA VID VSB WfM ZIF 321 Local Area Network Light Emitting Diode Low Pin Count Low Voltage Differential SAS Memory Repeater Hub – DDR-II Mean Time Between Failures Network Interface Card Original Equipment Manufacturer On-line Transaction Processing Opera
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HSC Firmware Update QSSC-S4R Technical Product Specification Reference Documents 322