Product guide

QSSC-S4R Server System Product Guide Appendix A: POST Codes
Version 1.0
161
Error
Code
Error Message Response
0x8130 Processor Disabled Major
0x8140 Processor FRB-3 timeout. Major
0x8160 Processor unable to apply microcode update. Major
0x8170 Processor Built-In Self Test (BIST) failure. Major
0x8180 Processor microcode update not found. Minor
0x8190 Watchdog Timer failed on last boot. Major
0x8198 OS boot watchdog timer failure. Major
0x8300 Baseboard Management Controller failed self test. Major
0x84F2 Baseboard Management Controller failed to respond. Major
0x84F3 Baseboard Management Controller in Update Mode. Major
0x84F4 Baseboard Management Controller Sensor Data Record empty. Major
0x84FF Baseboard Management Controller System Event Log full. Minor
0x8604 Chipset Reclaim of non critical variables complete. Minor
0xA000 TPM device not detected. Major
0xA001 TPM device is missing or not responding. Major
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system video initialization, the BIOS uses beep codes
to inform users about error conditions. The beep code is followed by a user visible code on POST Progress
LEDs.
Table 54. Beep Codes
Bee
p
s E
r
r
or Messa
g
e POST Pro
gr
ess Code Descri
p
tion
3 Memory error
System halted because a fatal error related to the
memory.
BMC Beep Codes
The BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the
problem is discovered (for example, on each power-up attempt), but are not sounded continuously. supported
codes are listed in Table 55. Each digit in the code is represented by a sequence of beeps whose count is equal
to the digit.
Table 55. BMC Beep Codes
Code Reason for Beep Associated Sensors Supported
1-5-2-1 No CPUs installed or first CPU socket is
empty.
CPU Missing Sensor Yes
1-5-4-2 Power fault: DC power unexpectedly lost
(power good dropout).
Power unit – power unit
failure offset.
Yes
1-5-4-4 Power control fault (power good assertion
timeout).
Power unit – soft power
control failure offset.
Yes