Technical information

Before You Begin: Important Concepts
XAPP1206 v1.1 June 12, 2014 www.xilinx.com 4
Figure 1 shows the single core Cortex-A9 processor block diagram.
One potential effect of the Cortex-A9 processor is the re-ordering of memory accesses. The
order in which load and store instructions are executed is not necessarily the same as the order
seen in disassembly. Hit-under-miss behaviors in cache mean that a load that goes into (hits)
the cache can complete before a load earlier in the program which missed the cache. Besides
load and store instructions, other instructions can also be executed out-of-order, as long as
there are no dependencies. This makes statically analyzing code sequences very impractical.
For NEON, even though the cycle timing information can be found in the ARM document, it is
difficult to determine how many cycles are needed even for a trivial piece of code. How
instructions move through the pipeline depends not only on the instruction sequence generated
by the compiler but also on the pattern of surrounding instructions. The memory system can
also have a significant effect on the movement of instructions through the pipeline.
Pending memory accesses (such as data loads/store instructions and instruction fetches) that
miss in the cache can stall instructions that are dependent on them for tens of cycles. In
extreme cases, for example, when Dynamic RAM contention or refresh conditions exist, the
latency can increase to hundreds of cycles. Standard data processing instructions usually take
only take one or two cycles, but this can be affected by many factors, and the theoretical
X-Ref Target - Figure 1
Figure 1: Single Core Cortex-A9 Processor Block Diagram
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