Product manual

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Figure 3 Data path from PCI Express to PMC ............................................................................................... 6
Figure 4 PCI Express side A......................................................................................................................... 11
Figure 5 PCI Express side B......................................................................................................................... 12
Figure 6 JN1, JN2, JN3 and JN4 .................................................................................................................. 13
Figure 9 Standard differential pairing........................................................................................................... 19
Figure 10 VITA 46 differential pairing ....................................................................................................... 20
Figure 7 68-pin connector numbering .......................................................................................................... 21
Figure 8 68-pin SCSI style with major dimensions ...................................................................................... 21
Figure 11 JTAG Factory jumper setting....................................................................................................... 22
Figure 12 GND and INTA connections........................................................................................................ 23
Figure 13 JP7 RS232 port............................................................................................................................. 24
Figure 14 RS232 cable diagrams.................................................................................................................. 25
Figure 15 Factory use only ........................................................................................................................... 26
Figure 16 Power supply architecture ........................................................................................................... 27
Figure 17 Thermal Frame and anti-fret parts................................................................................................ 29
Figure 18 Example of monitor setup ............................................................................................................ 30
Figure 19 Port settings for the PC ................................................................................................................ 30
Figure 20 Main screen-shot. ......................................................................................................................... 31
Figure 21 Voltages/Currents Monitored, temp. sensor locations. ................................................................ 32
Figure 22 Printed Circuit Placement Side B................................................................................................. 36
Figure 23 Printed Circuit Placement Side A................................................................................................. 36
Figure 24 Adjacent slot interference, dimensions in inches ......................................................................... 41
Tables
Table 1 - DIP switch S1 settings ................................................................................................................... 7
Table 2 PCI Express signals ......................................................................................................................... 10
Table 3 JN1 pinout ....................................................................................................................................... 14
Table 4 JN2 pinout ....................................................................................................................................... 15
Table 5 JN3 pinout ....................................................................................................................................... 16
Table 6 JN4 pinout ...................................................................................................................................... 17
Table 7 JTAG functions JP3......................................................................................................................... 22