Specifications

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List of Figures

1 Resolution Calculations for Conventionally Generated PWM......................................................... 7

2 Operating Logic Using MEP ............................................................................................... 9

3 HRPWM Extension Registers and Memory Configuration ........................................................... 10

4 HRPWM System Interface ............................................................................................... 11

5 Required PWM Waveform for a Requested Duty = 40.5% .......................................................... 13

6 Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ................................ 16

7 High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ................................ 18

8 Simple Buck Controlled Converter Using a Single PWM ............................................................ 24

9 PWM Waveform Generated for Simple Buck Controlled Converter ................................................ 24

10 Simple Reconstruction Filter for a PWM Based DAC ................................................................ 26

11 PWM Waveform Generated for the PWM DAC Function ............................................................ 26

12 HRPWM Configuration Register (HRCNFG)........................................................................... 30

13 Counter Compare A High Resolution Register (CMPAHR).......................................................... 30

14 TB Phase High Resolution Register (TBPHSHR)..................................................................... 30

List of Tables

1 Resolution for PWM and HRPWM........................................................................................ 7

2 HRPWM Registers ........................................................................................................ 10

3 Relationship Between MEP Steps, PWM Frequency and Resolution .............................................. 12

4 CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right)......................................................... 14

5 Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles ................................................. 17

6 SFO Library Routines..................................................................................................... 18

7 Factor Values .............................................................................................................. 21

8 Register Descriptions ..................................................................................................... 29

9 HRPWM Configuration Register (HRCNFG) Field Descriptions .................................................... 30

10 Counter Compare A High Resolution Register (CMPAHR) Field Descriptions ................................... 30

11 TB Phase High Resolution Register (TBPHSHR) Field Descriptions .............................................. 31

12 SFO Library Version Comparison ....................................................................................... 33

13 SFO V5 Library Routines................................................................................................. 34

14 Software Functions........................................................................................................ 36

15 Technical Changes in the Current Revision ........................................................................... 41

List of Figures SPRU924F– April 2005– Revised October 2011

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