Specifications

T =1000ns

PWM

EPWM1A

0 100

60ns

30ns

(F =1MHz)

PWM

3 6

SYSCLKOUT =

TBCLK=

100MHz

Operational Description of HRPWM

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NOTE: The MEP scale factor (MEP_ScaleFactor) varies with the system clock and DSP operating

conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which

uses the built in diagnostics in each HRPWM and returns the best scale factor for a given

operating point.

The scale factor varies slowly over a limited range so the optimizing C function can be run

very slowly in a background loop.

The CMPA and CMPAHR registers are configured in memory so that the 32-bit data

capability of the 28x CPU can write this as a single concatenated value, i.e.,

[CMPA:CMPAHR].

The mapping scheme has been implemented in both C and assembly, as shown in

Section 2.5. The actual implementation takes advantage of the 32-bit CPU architecture of the

28xx, and is somewhat different from the steps shown in Section 2.3.2.

For time critical control loops where every cycle counts, the assembly version is

recommended. This is a cycle optimized function (11 SYSCLKOUT cycles ) that takes a Q15

duty value as input and writes a single [CMPA:CMPAHR] value.

2.3.3 Duty Cycle Range Limitation

In high resolution mode, the MEP is not active for 100% of the PWM period. It becomes operational:

• 3 SYSCLK cycles after the period starts when diagnostics are disabled

• 6 SYSCLK cycles after the period starts when SFO diagnostics are running

Duty cycle range limitations are illustrated in Figure 6 . This limitation imposes a lower duty cycle limit on

the MEP. For example, precision edge control is not available all the way down to 0% duty cycle. Although

for the first 3 or 6 cycles, the HRPWM capabilities are not available, regular PWM duty control is still fully

operational down to 0% duty. In most applications this should not be an issue as the controller regulation

point is usually not designed to be close to 0% duty cycle. To better understand the useable duty cycle

range, see Table 5 .

Figure 6. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz

High-Resolution Pulse Width Modulator (HRPWM) SPRU924F– April 2005– Revised October 2011

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