Specifications

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Operational Description of HRPWM

Assumptions for this example:

System clock , SYSCLKOUT = 10 ns (100 MHz)

PWM frequency = 1.25 MHz (1/800 ns)

Required PWM duty cycle, PWMDuty = 0.405 (40.5%)

PWM period in terms of coarse steps, = 80

PWMperiod (800 ns/10 ns)

Number of MEP steps per coarse step at = 55

180 ps (10 ns /180 ps ), MEP_ScaleFactor

Value to keep CMPAHR within the range of

1-255 and fractional rounding constant

(default value) = 1.5 (0180h in Q8 format)

Step 1: Percentage Integer Duty value conversion for CMPA register

CMPA register value = int(PWMDuty*PWMperiod); int means integer part

= int(0.405*80 )

= int(32.4 )

CMPA register value = 32 (20h)

Step 2: Fractional value conversion for CMPAHR register

CMPAHR register value = (frac(PWMDuty*PWMperiod)*MEP_ScaleFactor

+1.5) << 8); frac means fractional part

= (frac(32.4) *55 + 1.5) <<8 Shift is to move the value as

CMPAHR high byte

= (0.4 * 55 + 1.5) <<8

= (22 + 1.5) <<8

= 23.5 * 256; Shifting left by 8 is the same as multiplying

by 256.

= 6016

CMPAHR value = 1780h CMPAHR value = 1700h , lower 8 bits will be

ignored by hardware.

SPRU924F– April 2005– Revised October 2011 High-Resolution Pulse Width Modulator (HRPWM)

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