TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator (HRPWM) Reference Guide Literature Number: SPRU924F April 2005 – Revised October 2011
SPRU924F – April 2005 – Revised October 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Contents Preface ....................................................................................................................................... 5 1 Introduction ........................................................................................................................ 7 2 Operational Description of HRPWM ....................................................................................... 9 ................................................................................ 10 .........
www.ti.com List of Figures 1 Resolution Calculations for Conventionally Generated PWM ......................................................... 7 2 Operating Logic Using MEP ............................................................................................... 9 3 HRPWM Extension Registers and Memory Configuration ........................................................... 10 4 HRPWM System Interface 5 Required PWM Waveform for a Requested Duty = 40.5% ....................................
Preface SPRU924F – April 2005 – Revised October 2011 Read This First About This Manual This document describes the operation of the high-resolution extension to the pulse width modulator (HRPWM) . The HRPWM module described in this reference guide is a Type 0 HRPWM. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with an HRPWM module of the same type, to determine the differences between types, and for a list of device-specific differences within a type.
Related Documentation From Texas Instruments www.ti.com SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRU716 — TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
Reference Guide SPRU924F – April 2005 – Revised October 2011 High-Resolution Pulse Width Modulator (HRPWM) This document is used in conjunction with the device-specific Enhanced Pulse Width Modulator (ePWM) Module Reference Guide. The HRPWM module extends the time resolution capabilities of the conventionally derived digital pulse width modulator (PWM). HRPWM is typically used when PWM resolution falls below ~ 9-10 bits.
Introduction www.ti.com Table 1. Resolution for PWM and HRPWM (continued) PWM Freq (kHz) Regular Resolution (PWM) High Resolution (HRPWM) Bits % Bits % 150 9.4 0.2 15.2 0.003 200 9.0 0.2 14.8 0.004 250 8.6 0.3 14.4 0.005 500 7.6 0.5 13.8 0.007 1000 6.6 1.0 12.4 0.018 1500 6.1 1.5 11.9 0.027 2000 5.6 2.0 11.4 0.036 Although each application may differ, typical low frequency PWM operation (below 250 kHz) may not require HRPWM.
Operational Description of HRPWM www.ti.com 2 Operational Description of HRPWM The HRPWM is based on micro edge positioner (MEP) technology. MEP logic is capable of positioning an edge very finely by sub-dividing one coarse system clock of a conventional PWM generator. The time step accuracy is on the order of 150 ps. See the device-specific data sheet for the typical MEP step size on a particular device.
Operational Description of HRPWM www.ti.com Table 2. HRPWM Registers mnemonic Address Offset TBPHSHR 0x0002 No Extension Register for HRPWM Phase (8 bits) CMPAHR 0x0008 Yes Extension Register for HRPWM Duty (8 bits) HRCNFG (1) 0x0020 No HRPWM Configuration Register (1) 2.1 Shadowed Description This register is EALLOW protected. Controlling the HRPWM Capabilities The MEP of the HRPWM is controlled by two extension registers, each 8-bits wide.
Operational Description of HRPWM www.ti.com Figure 4.
Operational Description of HRPWM 2.3 www.ti.com Principle of Operation The MEP logic is capable of placing an edge in one of 255 (8 bits) discrete time steps (see device-specific data sheet for typical MEP step size). The MEP works with the TBM and CCM registers to be certain that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of PWM frequencies, system clock frequencies and other operating conditions.
Operational Description of HRPWM www.ti.com 2.3.1 Edge Positioning In a typical power control loop (e.g., switch modes, digital motor control [DMC], uninterruptible power supply [UPS]), a digital controller (PID, 2pole/2zero, lag/lead, etc.) issues a duty command, usually expressed in a per unit or percentage terms. Assume that for a particular operating point, the demanded duty cycle is 0.405 or 40.5% on time and the required converter PWM frequency is 1.25 MHz.
Operational Description of HRPWM www.ti.com Table 4. CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) CMPA (count) (1) (2) (3) DUTY % High Time (ns) CMPA (count) CMPAHR (count) Duty (%) High Time (ns) 28 35.0 280 32 18 40.405 323.24 29 36.3 290 32 19 40.428 323.42 30 37.5 300 32 20 40.450 323.60 31 38.8 310 32 21 40.473 323.78 32 40.0 320 32 22 40.495 323.96 33 41.3 330 32 23 40.518 324.14 34 42.5 340 32 24 40.540 324.32 32 25 40.563 324.
Operational Description of HRPWM www.ti.com Assumptions for this example: System clock , SYSCLKOUT PWM frequency Required PWM duty cycle, PWMDuty PWM period in terms of coarse steps, PWMperiod (800 ns/10 ns) Number of MEP steps per coarse step at 180 ps (10 ns /180 ps ), MEP_ScaleFactor Value to keep CMPAHR within the range of 1-255 and fractional rounding constant (default value) = = = = 10 ns (100 MHz) 1.25 MHz (1/800 ns) 0.405 (40.5%) 80 = 55 = 1.
Operational Description of HRPWM www.ti.com NOTE: The MEP scale factor (MEP_ScaleFactor) varies with the system clock and DSP operating conditions. TI provides an MEP scale factor optimizing (SFO) software C function, which uses the built in diagnostics in each HRPWM and returns the best scale factor for a given operating point. The scale factor varies slowly over a limited range so the optimizing C function can be run very slowly in a background loop.
Operational Description of HRPWM www.ti.com Table 5. Duty Cycle Range Limitation for 3 and 6 SYSCLK/TBCLK Cycles (1) PWM Frequency (1) (kHz) 3 Cycles Minimum Duty 6 Cycles SYSCLKOUT Minimum Duty 200 0.6% 1.2% 400 1.2% 2.4% 600 1.8% 3.6% 800 2.4% 4.8% 1000 3.0% 6.0% 1200 3.6% 7.2% 1400 4.2% 8.4% 1600 4.8% 9.6% 1800 5.4% 10.8% 2000 6.0% 12.
Operational Description of HRPWM www.ti.com Figure 7. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz Tpwm = 1000 ns (Fpwm = 1 MHz) 60 ns 30 ns SYSCLKOUT = 100 MHz 0 3 100 6 EPWM1A 2.4 Scale Factor Optimizing Software (SFO) The micro edge positioner (MEP) logic is capable of placing an edge in one of 255 discrete time steps. As previously mentioned, the size of these steps is on the order of 150 ps (see device-specific data sheet for typical MEP step size on your device).
Operational Description of HRPWM www.ti.com Table 6. SFO Library Routines (continued) Function Description MEP steps per TBCLK = MEP_ScaleFactor[n] * (100/50) =66 * 2 = 132 (1) Constraints when using this function: SFO_MepDis(n) can be used with SYSCLKOUT from 50 MHz to maximum SYSCLK frequency. MEP diagnostics logic uses SYSCLKOUT not TBCLK and hence SYSCLKOUT restriction is an important constraint. SFO_MepDis(n) function does not require a starting Scale Factor value.
Operational Description of HRPWM www.ti.com While using HRPWM feature with no SFO diagnostics, HRPWM logic will not be active for the first 3 TBCLK cycles of the PWM period. While running the application in this configuration, if CMPA register value is less than 3 cycles, then its CMPAHR register must be cleared to zero. This would avoid any unexpected transitions on PWM signal.
Operational Description of HRPWM www.ti.com Table 7.
Operational Description of HRPWM www.ti.com Example 3. Initializing With a Scale Factor Value (continued) while (MEP_ScaleFactor[3] == 0) SFO_MepDis(3); //SFO for HRPWM3 while (MEP_ScaleFactor[4] == 0) SFO_MepDis(4); //SFO for HRPWM4 // Initialize a common seed variable MEP_ScaleFactor[0] // required for all SFO functions MEP_ScaleFactor[0] = MEP_ScaleFactor[1]; // Common variable for SFOMepEn(n) function Step 4.
Operational Description of HRPWM www.ti.com Example 4.
Operational Description of HRPWM www.ti.com Example 5.
Operational Description of HRPWM www.ti.com The example code shown consists of two main parts: • Initialization code (executed once) • Run time code (typically executed within an ISR) Example 6 shows the Initialization code. The first part is configured for conventional PWM. The second part sets up the HRPWM resources. This example assumes MEP step size of 150 ps and does not use the SFO library. Example 6.
Operational Description of HRPWM www.ti.com Example 7.
Operational Description of HRPWM www.ti.com Example 8. PWM DAC Function Initialization Code void HrPwmDacDrvCnf(void) { // Config for conventional PWM first EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; EPwm1Regs.TBPRD = 250; hrDAC_period = 250; // Set Immediate load // Period set for 400 kHz PWM // Used for Q15 to Q0 scaling EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; EPwm1Regs.TBCTL.bit.
Operational Description of HRPWM www.ti.com Example 9. PWM DAC Function Run-Time Code EPWM1_BASE .set 0x6800 CMPAHR1 .
HRPWM Register Descriptions www.ti.com 3 HRPWM Register Descriptions This section describes the applicable HRPWM registers 3.1 Register Summary A summary of the registers required for the HRPWM is shown in the table below. Table 8.
HRPWM Register Descriptions 3.2 www.ti.com Registers and Field Descriptions Figure 12. HRPWM Configuration Register (HRCNFG) 15 8 Reserved R-0 7 3 2 Reserved 4 HRLOAD CTLMODE 1 EDGMODE 0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9.
HRPWM Register Descriptions www.ti.com Table 11. TB Phase High Resolution Register (TBPHSHR) Field Descriptions Bit Field Value Description 15-8 TBPHSH Time base phase high resolution bits 7-0 Reserved Any writes to these bit(s) must always have a value of 0.
High-Resolution Pulse Width Modulator (HRPWM) SPRU924F – April 2005 – Revised October 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated
Appendix A www.ti.com Appendix A SFO Library Software - SFO_TI_Build_V5.lib This appendix includes a detailed description of the software routines in SFO_TI_Build_V5.lib which supports up to 16 HRPWM channels. A.1 SFO Library Version Comparison Table 12 includes a high-level comparison between SFO_TI_Build.lib and SFO_TI_V5.lib. A detailed description of SFO_TI_Build_V5.lib follows the table, and more information on SFO_TI_Build.lib can be found in Section 2.4. Table 12.
SFO Library Version Comparison www.ti.com Table 13. SFO V5 Library Routines Function int SFO_MepDis_V5(n) Description Scale Factor Optimizer V5 with MEP Disabled This routine is very similar to the SFO_MepDis() routine in the original SFO library, but with one change. It now returns a 1 when MEP-disabled calibration is complete, or a 0 while calibration is still running.
SFO Library Version Comparison www.ti.com Table 13. SFO V5 Library Routines (continued) Function Description Constraints when using this function: • This routine must be run on one channel at a time and cannot be run on multiple channels concurrently. When it has finished updating the MEP_ScaleFactor for a channel, it will return a 1. If it is still calibrating, it will return a 0. A background loop should exist in the user code which calls SFO_MepEn_V5(n) repeatedly until it returns a 1.
Software Usage www.ti.com Table 13. SFO V5 Library Routines (continued) Function Description If it returns a 2, the MEP_ScaleFactor for the channel has finished updating and is outside the typical drift range of MEP_ScaleFactor[0] +/- 15 even with large temperature and voltage variaitions.
Software Usage www.ti.com Step 1. Add "Include" Files The SFO_V5.h file needs to be included as follows. This include file is mandatory when using the SFO V5 library functions. For the TMS320F28044 device, the C2804x C/C++ Header Files and Peripheral Examples (literature number SPRC324) DSP2804x_Device.h and DSP2804x_PWM_defines.h files are necessary as will, as they are used by all TI software examples for the device. These file names will change in accordance with your specific device.
Software Usage www.ti.com &EPwm8Regs, &EPwm9Regs, &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, & EPwm13Regs, &EPwm14Regs, &EPwm15Regs, &EPwm16Regs}; 38 SFO Library Software - SFO_TI_Build_V5.
Software Usage www.ti.com Step 4. MEP_ScaleFactor After power up, the SFO_MepEn_V5(n) function needs a typical scale factor starting seed value in MEP_ScaleFacter[0]. This value can be conveniently determined using one of the ePWM modules to run the SFO_MepDis_V5(n) function prior to initializing the PWM settings for the application. The SFO_MepDis_V5(n) function does not require a starting scale factor value.
Software Usage www.ti.com for(i=1; i<(PWM_CH-1); i++) //update scale factors for ePWM 1-15 { MEP_ScaleFactor[i] = MEP_ScaleFactor[16]; } NOTE: See the hrpwm_sfo_v5 example in your device-specific Header Files and Peripheral Examples software package available on the TI website. 40 SFO Library Software - SFO_TI_Build_V5.
www.ti.com Appendix B Revision History This document was revised and lists only revisions made in this most recent version. The scope of the revisions was limited to technical changes as shown in Table 15. Table 15.
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