TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide Literature Number: SPRU791F November 2004 – Revised July 2009
SPRU791F – November 2004 – Revised July 2009 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 9 1 1.1 1.2 1.3 ............................................................................................................. 13 Introduction .................................................................................................................. 14 Submodule Overview .......................................................................................
www.ti.com 4 ............................................................................................ 3.1 Overview of Multiple Modules 3.2 Key Configuration Capabilities............................................................................................ 72 3.3 Controlling Multiple Buck Converters With Independent Frequencies .............................................. 73 3.4 Controlling Multiple Buck Converters With Same Frequencies ..................................................
www.ti.com List of Figures 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 Multiple ePWM Modules................................................................................................... Submodules and Signal Connections for an ePWM Module .........................................................
www.ti.com 2-43 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 6 Event-Trigger SOCB Pulse Generator .................................................................................. 70 Simplified ePWM Module..................................................................................................
www.ti.com List of Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 A-1 ePWM Module Control and Status Register Set Grouped by Submodule .......................................... 18 Submodule Configuration Parameters...................................................................................
List of Tables SPRU791F – November 2004 – Revised July 2009 Submit Documentation Feedback
Preface SPRU791F – November 2004 – Revised July 2009 Read This First The Enhanced Pulse Width Modulator (ePWM) module described in this reference guide is a Type 0 ePWM. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for a list of all devices with a ePWM module of the same type, to determine the differences between the types, and for a list of device-specific differences within a type.
Related Documentation From Texas Instruments www.ti.
www.ti.com Related Documentation From Texas Instruments SPRAA85 — Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define macros and topics of code efficiency and special case registers are also addressed.
Read This First SPRU791F – November 2004 – Revised July 2009 Submit Documentation Feedback
Chapter 1 SPRU791F – November 2004 – Revised July 2009 Introduction The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipments. These systems include digital motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of power conversion.
Introduction 1.1 www.ti.com Introduction An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis.
Submodule Overview www.ti.com Figure 1-1. Multiple ePWM Modules xSYNCI SYNCI EPWM1INT EPWM1A EPWM1SOC ePWM1 module EPWM1B SYNCO xSYNCO To eCAP1 SYNCI EPWM2INT EPWM2SOC PIE EPWM2A ePWM2 module EPWM2B GPIO MUX SYNCO SYNCI EPWMxINT EPWMxSOC EPWMxA ePWMx module EPWMxB TZ1 to TZ6 SYNCO xSOC ADC Peripheral Frame 1 The order in which the ePWM modules are connected may differ from what is shown in Figure 1-1. See Section 2.2.3.2 for the synchronization scheme for a particular device.
Submodule Overview www.ti.com Figure 1-2. Submodules and Signal Connections for an ePWM Module EPWMxSYNCI EPWMxSYNCO ePWM module Time-base (TB) module Counter-compare (CC) module PIE EPWMxTZINT EPWMxINT Action-qualifier (AQ) module Dead-band (DB) module ADC EPWMxSOCA EPWMxSOCB PWM-chopper (PC) module TZ1 to TZ6 EPWMxA EPWMxB GPIO MUX Event-trigger (ET) module Peripheral bus Trip-zone (TZ) module Figure 1-3 shows more internal details of a single ePWM module.
Register Mapping www.ti.com Figure 1-3.
Register Mapping www.ti.com Table 1-1.
Chapter 2 SPRU791F – November 2004 – Revised July 2009 ePWM Submodules Seven submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software. Topic 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 .................................................................................................. Overview .................................................................................. Time-Base (TB) Submodule ..........................................
Overview 2.1 www.ti.com Overview Table 2-1 lists the seven key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Section 2.3 for relevant details. Table 2-1. Submodule Configuration Parameters Submodule 20 Configuration Parameter or Option Time-base (TB) • Scale the time-base clock (TBCLK) relative to the system clock (SYSCLKOUT).
Overview www.ti.com Table 2-1. Submodule Configuration Parameters (continued) Submodule Event-trigger (ET) Configuration Parameter or Option • Enable the ePWM events that will trigger an interrupt. • Enable ePWM events that will trigger an ADC start-of-conversion event.
Overview www.ti.com Example 2-1.
Time-Base (TB) Submodule www.ti.com 2.2 Time-Base (TB) Submodule Each ePWM module has its own time-base submodule that determines all of the event timing for the ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work together as a single system. Figure 2-1 illustrates the time-base module's place within the ePWM. Figure 2-1.
Time-Base (TB) Submodule www.ti.com 2.2.2 Controlling and Monitoring the Time-base Submodule Table 2-2 shows the registers used to control and monitor the time-base submodule. Table 2-2.
Time-Base (TB) Submodule www.ti.com Table 2-3. Key Time-Base Signals Signal Description EPWMxSYNCI Time-base synchronization input. Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed from another ePWM peripheral.
Time-Base (TB) Submodule www.ti.com Figure 2-3. Time-Base Frequency and Period TPWM 4 PRD 4 4 3 3 2 3 2 1 2 1 0 Z 1 0 0 For Up Count and Down Count TPWM PRD 4 4 4 3 TPWM = (TBPRD + 1) x TTBCLK FPWM = 1/ (TPWM) 3 2 3 2 1 2 1 0 1 Z 0 0 TPWM TPWM 4 3 3 1 3 2 2 1 0 2.2.3.
Time-Base (TB) Submodule www.ti.com 2.2.3.2 Time-Base Counter Synchronization A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. The possible synchronization connections for the remaining ePWM modules are shown in Figure 2-4, Figure 2-5, and Figure 2-6.
Time-Base (TB) Submodule www.ti.com Scheme 2 shown in Figure 2-5 is used by the 2804x devices when the ePWM pinout is configured for A-channel only mode (GPAMCFG[EPWMMODE] = 3). If the 2804x ePWM pinout is configured for 280x compatible mode (GPAMCFG[EPWMMODE] = 0), then Scheme 1 is used. Figure 2-5.
Time-Base (TB) Submodule www.ti.com Scheme 3, shown in Figure 2-6, is used by all other devices. Figure 2-6.
Time-Base (TB) Submodule www.ti.com ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of the time-base counter immediately after a synchronization event. The new direction is independent of the direction prior to the synchronization event. The PHSDIR bit is ignored in count-up or count-down modes. See Figure 2-7 through Figure 2-10 for examples.
Time-Base (TB) Submodule www.ti.com Figure 2-7. Time-Base Up-Count Mode Waveforms TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max Figure 2-8.
Time-Base (TB) Submodule www.ti.com Figure 2-9. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0x0000 EPWMxSYNCI UP UP UP UP CTR_dir DOWN DOWN DOWN CTR = zero CTR = PRD CNT_max Figure 2-10.
Counter-Compare (CC) Submodule www.ti.com 2.3 Counter-Compare (CC) Submodule Figure 2-11 illustrates the counter-compare submodule within the ePWM. Figure 2-11.
Counter-Compare (CC) Submodule www.ti.com 2.3.2 Controlling and Monitoring the Counter-Compare Submodule The counter-compare submodule operation is controlled and monitored by the registers shown in Table 2-4: Table 2-4. Counter-Compare Submodule Registers Address Offset Shadowed CMPCTL Register Name 0x0007 No Counter-Compare Control Register.
Counter-Compare (CC) Submodule www.ti.com 2.3.3 Operational Highlights for the Counter-Compare Submodule The counter-compare submodule is responsible for generating two independent compare events based on two compare registers: 1. CTR = CMPA: Time-base counter equal to counter-compare A register (TBCTR = CMPA). 2. CTR = CMPB: Time-base counter equal to counter-compare B register (TBCTR = CMPB). For up-count or down-count mode, each event occurs only once per cycle.
Counter-Compare (CC) Submodule www.ti.com Figure 2-13. Counter-Compare Event Waveforms in Up-Count Mode TBCTR[15:0] 0xFFFF TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPA CTR = CMPB NOTE: An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count sequence. This can lead to a compare event being skipped. This skipping is considered normal operation and must be taken into account. Figure 2-14.
Counter-Compare (CC) Submodule www.ti.com Figure 2-15. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On Synchronization Event TBCTR[15:0] 0xFFFF TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPB CTR = CMPA Figure 2-16.
Action-Qualifier (AQ) Submodule 2.4 www.ti.com Action-Qualifier (AQ) Submodule Figure 2-17 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. Figure 2-17.
Action-Qualifier (AQ) Submodule www.ti.com The action-qualifier submodule is based on event-driven logic. It can be thought of as a programmable cross switch with events at the input and actions at the output, all of which are software controlled via the set of registers shown in Table 2-6. Figure 2-18.
Action-Qualifier (AQ) Submodule www.ti.com Actions are specified independently for either output (EPWMxA or EPWMxB). Any or all events can be configured to generate actions on a given output. For example, both CTR = CMPA and CTR = CMPB can operate on output EPWMxA. All qualifier actions are configured via the control registers found at the end of this section. For clarity, the drawings in this document use a set of symbolic actions. These symbols are summarized in Figure 2-19.
Action-Qualifier (AQ) Submodule www.ti.com 2.4.3 Action-Qualifier Event Priority It is possible for the ePWM action qualifier to receive more than one event at the same time. In this case events are assigned a priority by the hardware. The general rule is events occurring later in time have a higher priority and software forced events always have the highest priority. The event priority levels for up-down-count mode are shown in Table 2-8.
Action-Qualifier (AQ) Submodule www.ti.com Table 2-11. Behavior if CMPA/CMPB is Greater than the Period (continued) Counter Mode Compare on Up-Count Event CAD/CBD Down-Count Mode Never occurs. Compare on Down-Count Event CAD/CBD If CMPA/CMPB < TBPRD, the event will occur on a compare match (TBCTR=CMPA or CMPB). If CMPA/CMPB ≥ TBPRD, the event will occur on a period match (TBCTR=TBPRD).
Action-Qualifier (AQ) Submodule www.ti.com When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system. Figure 2-20.
Action-Qualifier (AQ) Submodule www.ti.com Figure 2-21. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB—Active High TBCTR TBPRD value Z P CB CA Z P CB CA Z P Z P CB CA Z P CB CA Z P EPWMxA EPWMxB A PWM period = (TBPRD + 1 ) × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active high (that is, high time duty proportional to CMPA).
Action-Qualifier (AQ) Submodule www.ti.com Figure 2-22. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active Low TBCTR TBPRD value P CA P CA P EPWMxA P CB P CB P EPWMxB A PWM period = (TBPRD + 1 ) × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). C Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
Action-Qualifier (AQ) Submodule www.ti.com Example 2-3. Code Sample for Figure 2-22 // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 350; // Compare A = 350 TBCLK counts EPwm1Regs.CMPB = 200; // Compare B = 200 TBCLK counts EPwm1Regs.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0; // clear TB counter EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.
www.ti.com Action-Qualifier (AQ) Submodule Example 2-4. Code Sample for Figure 2-23 // Initialization Time // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts EPwm1Regs.CMPA.half.CMPA = 200; // Compare A = 200 TBCLK counts EPwm1Regs.CMPB = 400; // Compare B = 400 TBCLK counts EPwm1Regs.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0; // clear TB counter EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; EPwm1Regs.TBCTL.bit.
Action-Qualifier (AQ) Submodule www.ti.com Figure 2-24. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Active Low TBCTR TBPRD value CA CA CA CA EPWMxA CB CB CB CB EPWMxB A PWM period = 2 x TBPRD × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low (that is, the low time duty is proportional to CMPA). C Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB).
Action-Qualifier (AQ) Submodule www.ti.com Figure 2-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and EPWMxB — Complementary TBCTR TBPRD value CA CA CA CA EPWMxA CB CB CB CB EPWMxB A PWM period = 2 × TBPRD × TTBCLK B Duty modulation for EPWMxA is set by CMPA, and is active low, i.e., low time duty proportional to CMPA C Duty modulation for EPWMxB is set by CMPB and is active high, i.e.
Action-Qualifier (AQ) Submodule www.ti.com Figure 2-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active Low TBCTR CA CA CB CB EPWMxA Z P Z P EPWMxB A PWM period = 2 × TBPRD × TBCLK B Rising edge and falling edge can be asymmetrically positioned within a PWM cycle. This allows for pulse placement techniques. C Duty modulation for EPWMxA is set by CMPA and CMPB. D Low time duty for EPWMxA is proportional to (CMPA + CMPB).
Dead-Band Generator (DB) Submodule www.ti.com 2.5 Dead-Band Generator (DB) Submodule Figure 2-27 illustrates the dead-band submodule within the ePWM module. Figure 2-27.
Dead-Band Generator (DB) Submodule www.ti.com 2.5.3 Operational Highlights for the Dead-Band Submodule The following sections provide the operational highlights. The dead-band submodule has two groups of independent selection options as shown in Figure 2-28. • Input Source Selection: The input signals to the dead-band module are the EPWMxA and EPWMxB output signals from the action-qualifier. In this section they will be referred to as EPWMxA In and EPWMxB In.
Dead-Band Generator (DB) Submodule www.ti.com • action-qualifier submodule to generate the signal as shown for EPWMxA. Mode 6: Bypass rising-edge-delay and Mode 7: Bypass falling-edge-delay Finally the last two entries in Table 2-13 show combinations where either the falling-edge-delay (FED) or rising-edge-delay (RED) blocks are bypassed. Table 2-13.
Dead-Band Generator (DB) Submodule www.ti.com Figure 2-29 shows waveforms for typical cases where 0% < duty < 100%. Figure 2-29.
Dead-Band Generator (DB) Submodule www.ti.com The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED) delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is delayed by.
PWM-Chopper (PC) Submodule 2.6 www.ti.com PWM-Chopper (PC) Submodule Figure 2-30 illustrates the PWM-chopper (PC) submodule within the ePWM module. Figure 2-30.
PWM-Chopper (PC) Submodule www.ti.com Figure 2-31. PWM-Chopper Submodule Operational Details Bypass 0 EPWMxA Start EPWMxA One shot OSHT PWMA_ch 1 Clk Pulse-width SYSCLKOUT /8 PCCTL [OSHTWTH] PCCTL [OSHTWTH] Pulse-width Divider and duty control PCCTL [CHPEN] PSCLK PCCTL[CHPFREQ] PCCTL[CHPDUTY] Clk One shot EPWMxB PWMB_ch 1 OSHT EPWMxB Start Bypass 0 2.6.4 Waveforms Figure 2-32 shows simplified waveforms of the chopping action only; one-shot and duty-cycle control are not shown.
PWM-Chopper (PC) Submodule 2.6.4.1 www.ti.com One-Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values. The width or period of the first pulse is given by: T1stpulse = TSYSCLKOUT × 8 × OSHTWTH Where TSYSCLKOUT is the period of the system clock (SYSCLKOUT) and OSHTWTH is the four control bits (value from 1 to 16) Figure 2-33 shows the first and subsequent sustaining pulses and Table 7.3 gives the possible pulse width values for a SYSCLKOUT = 100 MHz.
PWM-Chopper (PC) Submodule www.ti.com 2.6.4.2 Duty Cycle Control Pulse transformer-based gate drive designs need to comprehend the magnetic properties or characteristics of the transformer and associated circuitry. Saturation is one such consideration. To assist the gate drive designer, the duty cycles of the second and subsequent pulses have been made programmable.
Trip-Zone (TZ) Submodule 2.7 www.ti.com Trip-Zone (TZ) Submodule Figure 2-35 shows how the trip-zone (TZ) submodule fits within the ePWM module. Figure 2-35.
Trip-Zone (TZ) Submodule www.ti.com 2.7.2 Controlling and Monitoring the Trip-Zone Submodule The trip-zone submodule operation is controlled and monitored through the following registers: Table 2-17.
Trip-Zone (TZ) Submodule www.ti.com Table 2-18. Possible Actions On a Trip Event TZCTL[TZA] and/or TZCTL[TZB] EPWMxA and/or EPWMxB Comment 0,0 High-Impedance Tripped 0,1 Force to High State Tripped 1,0 Force to Low State Tripped 1,1 No Change Do Nothing. No change is made to the output. Example 2-8. Trip-Zone Configurations Scenario A: A one-shot trip event on TZ1 pulls both EPWM1A, EPWM1B low and also forces EPWM2A and EPWM2B high.
Trip-Zone (TZ) Submodule www.ti.com 2.7.4 Generating Trip Event Interrupts Figure 2-36 and Figure 2-37 illustrate the trip-zone submodule control and interrupt logic, respectively. Figure 2-36.
Event-Trigger (ET) Submodule www.ti.com Figure 2-37. Trip-Zone Submodule Interrupt Logic TZFLG[INT] TZCLR[INT] TZFLG[CBC] Clear Clear Latch TZCLR[CBC] Latch Set Set TZEINT[CBC] CBC trip event TZFLG[OST] EPWMx_TZINT (PIE) Generate interrupt pulse when input=1 Clear Latch Set TZEINT[OST] 2.
www.ti.com Event-Trigger (ET) Submodule 2.8.1 Operational Overview of the Event-Trigger Submodule The following sections describe the event-trigger submodule's operational highlights. Each ePWM module has one interrupt request line connected to the PIE and two start of conversion signals (one for each sequencer) connected to the ADC module. As shown in Figure 2-39, ADC start of conversion for all ePWM modules are ORed together and hence multiple modules can initiate an ADC start of conversion.
Event-Trigger (ET) Submodule www.ti.com Figure 2-39.
Event-Trigger (ET) Submodule www.ti.
Event-Trigger (ET) Submodule www.ti.com Figure 2-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs clear CTR=Zero Event Trigger Module Logic CTR=PRD EPWMxINTn PIE count CTRU=CMPA CTR=CMPA clear ETSEL reg CTRD=CMPA Direction qualifier CTR=CMPB /n CTRU=CMPB /n EPWMxSOCA ETPS reg count CTRD=CMPB ETFLG reg ADC clear EPWMxSOCB ETCLR reg /n CTR_dir ETFRC reg count The key registers used to configure the event-trigger submodule are shown in Table 2-19: Table 2-19.
Event-Trigger (ET) Submodule www.ti.com The number of events that have occurred can be read from the interrupt event counter (ETPS[INTCNT]) register bits. That is, when the specified event occurs the ETPS[INTCNT] bits are incremented until they reach the value specified by ETPS[INTPRD]. When ETPS[INTCNT] = ETPS[INTPRD] the counter stops counting and its output is set. The counter is only cleared when an interrupt is sent to the PIE.
Event-Trigger (ET) Submodule www.ti.com Figure 2-42. Event-Trigger SOCA Pulse Generator ETCLR[SOCA] Clear Latch ETFLG[SOCA] Set ETPS[SOCACNT] ETSEL[SOCASEL] Generate SOC pulse when input = 1 SOCA Clear CNT ETFRC[SOCA] 2-bit Counter 000 001 010 011 100 101 101 111 Inc CNT ETSEL[SOCAEN] ETPS[SOCAPRD] 0 CTR=Zero CTR=PRD 0 CTRU=CMPA CTRD=CMPA CTRU=CMPB CTRD=CMPB Figure 2-43 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator.
Chapter 3 SPRU791F – November 2004 – Revised July 2009 Applications to Power Topologies An ePWM module has all the local resources necessary to operate completely as a standalone module or to operate in synchronization with other identical ePWM modules. Topic 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 .................................................................................................. Overview of Multiple Modules ....................................................
Overview of Multiple Modules 3.1 www.ti.com Overview of Multiple Modules Previously in this user's guide, all discussions have described the operation of a single module. To facilitate the understanding of multiple modules working together in a system, the ePWM module described in reference is represented by the more simplified block diagram shown in Figure 3-1.
Controlling Multiple Buck Converters With Independent Frequencies www.ti.com Figure 3-2. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave Ext SyncIn (optional) Master Slave Phase reg SyncIn Phase reg EN Φ=0° 3.3 Φ=0° EPWM1A EPWM1B CTR=0 CTR=CMPB X 1 SyncIn EN SyncOut EPWM2A EPWM2B CTR=0 CTR=CMPB X 2 SyncOut Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck.
Controlling Multiple Buck Converters With Independent Frequencies www.ti.com Figure 3-3. Control of Four Buck Stages.
Controlling Multiple Buck Converters With Independent Frequencies www.ti.com Figure 3-4.
Controlling Multiple Buck Converters With Independent Frequencies www.ti.com Example 3-1. Configuration for Example in Figure 3-4 //===================================================================== // (Note: code for only 3 modules shown) // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; // Period = 1201 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode EPwm1Regs.
Controlling Multiple Buck Converters With Same Frequencies www.ti.com 3.4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules remain locked. Figure 3-5 shows such a configuration; Figure 3-6 shows the waveforms generated by the configuration. Figure 3-5. Control of Four Buck Stages.
Controlling Multiple Buck Converters With Same Frequencies www.ti.com Figure 3-6.
www.ti.com Controlling Multiple Buck Converters With Same Frequencies Example 3-2. Code Snippet for Configuration in Figure 3-5 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; // Period = 1200 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.
Controlling Multiple Half H-Bridge (HHB) Converters 3.5 www.ti.com Controlling Multiple Half H-Bridge (HHB) Converters Topologies that require control of multiple switching elements can also be addressed with these same ePWM modules. It is possible to control a Half-H bridge stage with a single ePWM module. This control can be extended to multiple stages. Figure 3-7 shows control of two synchronized Half-H bridge stages where stage 2 can operate at integer multiple (N) frequencies of stage 1.
Controlling Multiple Half H-Bridge (HHB) Converters www.ti.com Figure 3-8.
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) www.ti.com Example 3-3. Code Snippet for Configuration in Figure 3-7 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 600; // Period = 1200 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) www.ti.com Figure 3-9.
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) www.ti.com Figure 3-10.
www.ti.com Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) Example 3-4. Code Snippet for Configuration in Figure 3-9 //===================================================================== // Configuration //===================================================================== // Initialization Time //========================// EPWM Module 1 config EPwm1Regs.TBPRD = 800; // Period = 1600 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.
Practical Applications Using Phase Control Between PWM Modules 3.7 www.ti.com Practical Applications Using Phase Control Between PWM Modules So far, none of the examples have made use of the phase register (TBPHS). It has either been set to zero or its value has been a don't care. However, by programming appropriate values into TBPHS, multiple PWM modules can address another class of power topologies that rely on phase relationship between legs (or stages) for correct operation.
Controlling a 3-Phase Interleaved DC/DC Converter www.ti.com Figure 3-12. Timing Waveforms Associated With Phase Control Between 2 Modules FFFFh TBCTR[0-15] Master Module 600 600 TBPRD 0000 CTR = PRD (SycnOut) FFFFh time TBCTR[0-15] Φ2 Phase = 120° Slave Module TBPRD 600 600 200 TBPHS 200 0000 SyncIn 3.8 time Controlling a 3-Phase Interleaved DC/DC Converter A popular power topology that makes use of phase-offset between modules is shown in Figure 3-13.
Controlling a 3-Phase Interleaved DC/DC Converter www.ti.com Figure 3-13.
Controlling a 3-Phase Interleaved DC/DC Converter www.ti.com Figure 3-14.
Controlling a 3-Phase Interleaved DC/DC Converter www.ti.com Example 3-5. Code Snippet for Configuration in Figure 3-13 //===================================================================== // Config // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 450; // Period = 900 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode EPwm1Regs.TBCTL.bit.
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter www.ti.com 3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter The example given in Figure 3-15 assumes a static or constant phase relationship between legs (modules). In such a case, control is achieved by modulating the duty cycle. It is also possible to dynamically change the phase value on a cycle-by-cycle basis.
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter www.ti.com Figure 3-16.
www.ti.com Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter Example 3-6. Code Snippet for Configuration in Figure 3-15 //===================================================================== // Config //===================================================================== // Initialization Time //======================== // EPWM Module 1 config EPwm1Regs.TBPRD = 1200; // Period = 1201 TBCLK counts EPwm1Regs.CMPA = 600; // Set 50% fixed duty for EPWM1A EPwm1Regs.TBPHS.half.
Applications to Power Topologies SPRU791F – November 2004 – Revised July 2009 Submit Documentation Feedback
Chapter 4 SPRU791F – November 2004 – Revised July 2009 Registers This chapter includes the register layouts and bit description for the submodules. Topic 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 .................................................................................................. Page Time-Base Submodule Registers ................................................ 96 Counter-Compare Submodule Registers ...................................... 99 Action-Qualifier Submodule Registers ...............
Time-Base Submodule Registers 4.1 www.ti.com Time-Base Submodule Registers Figure 4-1 through Figure 4-5 and Table 4-1 through Table 4-5 provide the time-base register definitions. Figure 4-1. Time-Base Period Register (TBPRD) 15 0 TBPRD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-1. Time-Base Period Register (TBPRD) Field Descriptions Bits Name Value 15-0 TBPRD 0000- These bits determine the period of the time-base counter. This sets the PWM frequency.
Time-Base Submodule Registers www.ti.com Figure 4-4. Time-Base Control Register (TBCTL) 15 14 13 12 10 9 8 FREE, SOFT PHSDIR CLKDIV HSPCLKDIV R/W-0 R/W-0 R/W-0 R/W-0,0,1 7 6 3 2 HSPCLKDIV SWFSYNC 5 SYNCOSEL 4 PRDLD PHSEN 1 CTRMODE 0 R/W-0,0,1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions Bit 15:14 Field Value FREE, SOFT Description Emulation Mode Bits.
Time-Base Submodule Registers www.ti.com Table 4-4. Time-Base Control Register (TBCTL) Field Descriptions (continued) Bit Field 9:7 HSPCLKDIV Value Description High Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager (EV) peripheral.
Counter-Compare Submodule Registers www.ti.com Figure 4-5. Time-Base Status Register (TBSTS) 15 8 Reserved R-0 7 2 1 0 Reserved 3 CTRMAX SYNCI CTRDIR R-0 R/W1C-0 R/W1C-0 R-1 LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset Table 4-5.
Counter-Compare Submodule Registers www.ti.com Table 4-6. Counter-Compare A Register (CMPA) Field Descriptions Bits Name Description 15-0 CMPA The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions.
Counter-Compare Submodule Registers www.ti.com Figure 4-8. Counter-Compare Control Register (CMPCTL) 15 9 8 Reserved 10 SHDWBFULL SHDWAFULL R-0 R-0 R-0 1 0 7 6 5 4 Reserved SHDWBMODE Reserved SHDWAMODE 3 LOADBMODE 2 LOADAMODE R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-8.
Action-Qualifier Submodule Registers www.ti.com Figure 4-9. Compare A High Resolution Register (CMPAHR) 15 8 CMPAHR R/W-0 7 0 Reserved R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-9. Compare A High Resolution Register (CMPAHR) Field Descriptions Bit 15-8 Field Value CMPAHR 00-FFh These 8-bits contain the high-resolution portion (least significant 8-bits) of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write.
Action-Qualifier Submodule Registers www.ti.com Table 4-10. Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions (continued) Bits Name 7-6 CAD 5-4 3-2 Value Description Action when the counter equals the active CMPA register and the counter is decrementing. 00 Do nothing (action disabled) 01 Clear: force EPWMxA output low. 10 Set: force EPWMxA output high. 11 Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
Action-Qualifier Submodule Registers www.ti.com Table 4-11. Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions (continued) Bits Name 9-8 CBU 7-6 5-4 3-2 Value Description Action when the counter equals the active CMPB register and the counter is incrementing. 00 Do nothing (action disabled) 01 Clear: force EPWMxB output low. 10 Set: force EPWMxB output high. 11 Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
Action-Qualifier Submodule Registers www.ti.com Table 4-12. Action-Qualifier Software Force Register (AQSFRC) Field Descriptions Bit Field Value 15:8 Reserved 7:6 RLDCSF 5 Description AQCSFRC Active Register Reload From Shadow Options 00 Load on event counter equals zero 01 Load on event counter equals period 10 Load on event counter equals zero or counter equals period 11 Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register).
Dead-Band Submodule Registers www.ti.com Table 4-13. Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions (continued) Bits Name 3-2 CSFB Value Description Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC[RLDCSF]. 1-0 00 Forcing disabled, i.e.
Dead-Band Submodule Registers www.ti.com Table 4-14. Dead-Band Generator Control Register (DBCTL) Field Descriptions Bits Name Value Description 15-6 Reserved Reserved 5-4 IN_MODE Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays.
PWM-Chopper Submodule Control Register www.ti.com Figure 4-15. Dead-Band Generator Rising Edge Delay Register (DBRED) 15 10 9 8 Reserved DEL R-0 R/W-0 7 0 DEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-15. Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions Bits 15-10 9-0 Name Value Description Reserved Reserved DEL Rising Edge Delay Count. 10-bit counter. Figure 4-16.
PWM-Chopper Submodule Control Register www.ti.com Table 4-17. PWM-Chopper Control Register (PCCTL) Bit Descriptions Bits Name 15-11 Reserved 10-8 CHPDUTY 7:5 4:1 0 Value Description Reserved Chopping Clock Duty Cycle 000 Duty = 1/8 (12.5%) 001 Duty = 2/8 (25.0%) 010 Duty = 3/8 (37.5%) 011 Duty = 4/8 (50.0%) 100 Duty = 5/8 (62.5%) 101 Duty = 6/8 (75.0%) 110 Duty = 7/8 (87.5%) 111 Reserved CHPFREQ Chopping Clock Frequency 000 Divide by 1 (no prescale, = 12.
Trip-Zone Submodule Control and Status Registers 4.6 www.ti.com Trip-Zone Submodule Control and Status Registers Figure 4-18. Trip-Zone Select Register (TZSEL) 15 14 13 12 11 10 9 8 Reserved OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7 5 4 3 2 1 0 Reserved 6 CBC6 CBC5 CBC4 CBC3 CBC2 CBC1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-18.
Trip-Zone Submodule Control and Status Registers www.ti.com Table 4-18.
Trip-Zone Submodule Control and Status Registers www.ti.com Figure 4-20. Trip-Zone Enable Interrupt Register (TZEINT) 15 8 Reserved R -0 7 2 1 0 Reserved 3 OST CBC Reserved R-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-20.
Trip-Zone Submodule Control and Status Registers www.ti.com Table 4-21. Trip-Zone Flag Register (TZFLG) Field Descriptions (continued) Bits 1 Name Value Description CBC Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually cleared by the user.
Trip-Zone Submodule Control and Status Registers www.ti.com Figure 4-23. Trip-Zone Force Register (TZFRC) 15 8 Reserved R-0 7 2 1 0 Reserved 3 OST CBC Reserved R-0 R/W-0 R/W-0 R- 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after resetonly an hour Table 4-23. Trip-Zone Force Register (TZFRC) Field Descriptions Bits Name 15-3 Reserved Reserved OST Force a One-Shot Trip Event via Software 2 1 0 114 Registers Value 0 Writing of 0 is ignored. Always reads back a 0.
Digital Compare Submodule Registers www.ti.com 4.7 Digital Compare Submodule Registers 4.8 Event-Trigger Submodule Registers Figure 4-24 through Figure 4-28 and Table 4-24 through Table 4-28 describe the registers for the event-trigger submodule. Figure 4-24.
Event-Trigger Submodule Registers www.ti.com Table 4-24. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued) Bits Name 3 INTEN 2-0 Value Description Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation INTSEL ePWM Interrupt (EPWMx_INT) Selection Options 000 Reserved 001 Enable event time-base counter equal to zero.
Event-Trigger Submodule Registers www.ti.com Table 4-25. Event-Trigger Prescale Register (ETPS) Field Descriptions (continued) Bits 11-10 Name Description SOCACNT ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 9-8 00 No events have occurred. 01 1 event has occurred. 10 2 events have occurred. 11 3 events have occurred.
Event-Trigger Submodule Registers www.ti.com Figure 4-26. Event-Trigger Flag Register (ETFLG) 15 8 Reserved R-0 7 3 2 1 0 Reserved 4 SOCB SOCA Reserved INT R-0 R-0 R-0 R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-26.
Event-Trigger Submodule Registers www.ti.com Table 4-27. Event-Trigger Clear Register (ETCLR) Field Descriptions (continued) Bits Name Value Description 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCA] flag bit 1 Reserved Reserved 0 INT ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect.
Proper Interrupt Initialization Procedure 4.9 www.ti.com Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized. The proper procedure for initializing the ePWM peripheral is as follows: 1. Disable Global Interrupts (CPU INTM flag) 2. Disable ePWM Interrupts 3. Initialize Peripheral Registers 4. Clear Any Spurious ePWM Flags (including PIEIFR) 5.
Appendix A SPRU791F – November 2004 – Revised July 2009 Revision History The scope of the revision was limited to technical changes as shown in Table A-1. Table A-1. Changes for Revision Location Modifications, Additions, and Deletions Example 2-8 Changed all instances of ePWM1 to ePWM2 for the following: TZSEL[OSHT6] = 1: enables TZ6 as a one-shot event source for ePWM2 TZCTL[TZA] = 0: EPWM2A will be put into a high-impedance state on a trip event. TZCTL[TZB] = 3: EPWM2B will ignore the trip event.
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