Owners Manual

4865 Sterling Drive, Boulder, CO 80301 Introduction

PH: 1 (800) PSAUDIO service@psaudio.com www.psaudio.com 15-061-01-1

Rev D

Owner’s Reference DirectStream DAC

Introduction

If the switch is too slow it won’t keep up with the 5.6MHz signal used in this instrument. If

the switch doesn’t react in consistent times it will introduce jitter. Use of traditional CMOS

gates adds a lot of jitter as do cross-coupled totem-poled bipolar transistors. Instead,

DirectStream relies on high speed dierential video amps, which are essentially class A

switches, have their outputs either near the top rail or near the bottom power supply rail

(without ever saturating) and provide a very clean DSD switch.

For the all important low pass ltering requirements an active lter adds self noise even if it

is eectively lowering incoming noise. A unique and eective solution to this problem is a

passive lter. The design uses a carefully crafted high bandwidth audio transformer at the

output of the instrument for both galvanic isolation from the outside world as well as low

pass ltering.

The theory of operation, the rmware and the complex algorithms needed to execute a

design of this magnitude are daunting in their scale and scope. The actual hardware to

run the instrument is, perhaps, easier to grasp although no less critical to the perfected

performance.

Listed in this section are the highlights of the hardware, system’s overview and design

choices made to create an instrument of this caliber.

1. DirectStream runs from one master clock designed to

subtend all possible combinations of sub-clocks, from 44.1,

88.2, 48, 96, etc in order to eliminate the need for multiple

clocks that cause errors and problems associated when noise

from the unused clock propagates to the desired clock.

2. All sample rates supported are synchronously upsampled to 10x

the standard DSD sample rate and then back down to double

rate DSD (2 * 64 * 44.1kHz). There’s no need for other clocks to

interpret the inputs, no matter what their sample rate, because

of the instrument’s single clock architecture.

3. The path from the single master clock to its retiming ip-op

path is designed as short as possible and isolated from all other

clocking.

4. Connections between sections of the design have large

impedances, not only lots of power supply isolation, but also, for

example, 2k resistors in series with digital signals to slow down

the edges and lessen any noise transfer.

5. Similarly we run I

C, SPI and other control signals as slowly as

DirectStream

hardware and

design choices

One master

clock