Service manual
MVP3-SCH-001 1.0
MVP3
2
8
Wednesday, May 21, 2003
MRT, Inc.
Title
Size Document Number Rev
Date: Sheet
of
VDD2V
VDD
VDD
VDD
VDD
VDD
VAA2V
VDC2V
VDC2V
VAA3V
VAA3RGB
VDD3V
VAA2V
BL-ON0 6
RED-1
SCL3
VSYNC1
VDDCTRL 4
BLUE+1
GREEN-1
D-HSYNC 4
RED+1
D-DE2 4
IRQ-3
OB[0..23] 4
HFS3
D-SHCLK2 4
HSYNC1
GREEN+1
D-VSYNC 4
OA[0..23] 4
BLK-ADJ 6
BLUE-1
SDA3
LCD_VEE_A 4
AUDIO-ADJ 8
MV_RESET3
CPH1
OA3
OB4
OA10
OB9
OB16
OB15
OA12
OB22
OA6
OA18
OA1
OA8
OA21
CONFIG0
OB23
OB17
OA15
OB7
OA9
OB0
OA7
OB6
OB5
OA11
OB10
OB14
OB12
GND
OA22
OB19
CONFIG3
OB3
OB11
OA16
OA23
D-SHCLK2
OA19
OA17
CONFIG1
OB18
RLS
OB1
CONFIG2
OA20
OA2
OB2
OA0
OB8
OB13
INV1
SOG
OA13
GND
POL
OB20
VDC2V
OA14
OB21
OA5
OA4
CPH1
VREF
GND-ANA
MV_XT_1
MV_XT
D-SHCLK2
C18
22pF
C17
22pF
Y1
12MHZ
R26 NP
R28 NP
C140
33p
R39
NP
R33 NP
R27 10K
R38
10K
EC1
22uF/16V
R30 10K
R29 1K
R31 10K
EC3
22uF/16V
R34 22
R32 10K
C35
M22pF
C34
M22pF
R107 1M
R35 22
R37 33
R36 33
C26
33p
R45 22
R44 22
R43 22
R42 22
C20
0.1uF
R106
100
C21
4.7nF
C24
4.7nF
C23
10nF
C22
10nF
C25
4.7nF
U3
MV3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
16
CAP_VSYNC
BLU_INB_0
BLU_INB_1
BLU_INB_2
BLU_INB_3
BLU_INB_4
BLU_INB_5
BLU_INB_6
BLU_INB_7
DIVDD3V
DIVSS
GRN_INB_0/HDATA_0
GRN_INB_1/HDATA_1
GRN_INB_2/HDATA_2
GRN_INB_3/HDATA_3
GRN_INB_5
GRN_INB_6
GRN_INB_7
DCVDD2V
DCVSS
RED_INB_0
RED_INB_1
RED_INB_2
RED_INB_3
RED_INB_4
RED_INB_5
RED_INB_6
RED_INB_7
VDD3V
DGND
DTEST
VDD2V
VGA_VSYNC
VGA_HSYNC
VAA2A
GNDA
SOGIN
VAA3V
AGND
VREF
CP
CZ
VAA3B
BIN+
BIN-
AGNDB
BCLP
VTOP
VBOT
VAA3G
GIN+
GIN-
AGNDG
GCLP
TOUTP
TOUTM
VAA3R
RIN+
RIN-
AGNDR
RCLP
ADVDD3V
ADVSS
XTAL
XTALI
DCVSS
GPIO1
GPIO0
PWM1
STH1
STH8
LP
DCVDD2V
SHC
RLS/<DISP_DE>
POL/<DISP_VSYNC>
CPH1/<SHCLK>
INV1/<DISP_HSYNC>
DCVSS
DOBVSS
BLU_OUTB_7
BLU_OUTB_6
BLU_OUTB_5
BLU_OUTB_4
DOBVDD3V
BLU_OUTB_3
BLU_OUTB_2
BLU_OUTB_1
BLU_OUTB_0
DOBVSS
RED_OUTA_7
RED_OUTA_6
RED_OUTA_5
RED_OUTA_4
DCVDD2V
RED_OUTA_3
RED_OUTA_2
RED_OUTA_1
RED_OUTA_0
DCVSS
GRN_OUTA_7
GRN_OUTA_6
GRN_OUTA_5
GRN_OUTA_4
DOBVDD3V
GRN_OUTA_3
GRN_OUTA_2
GRN_OUTA_1
GRN_OUTA_0
DOBVSS
BLU_OUTA_7
BLU_OUTA_6
BLU_OUTA_5
BLU_OUTA_4
DOBVDD3V
BLU_OUTA_3
BLU_OUTA_2
BLU_OUTA_1
BLU_OUTA_0
CAP_HSYNC
CAP_HREF
TVCLK
IRQ#
SCS#/HFS#
SDA
SCL
RST
STV3
STV1
CPV
OE3/<CONFIG3>
OE2/<CONFIG2>
OE1/<CONFIG1>
CPH2
PWM0/<CONFIG0>
DCVDD2V
INV2/<LCD_VEE>
LCD_VDD
LCD_VBL
DCVSS
RED_OUTB_7
RED_OUTB_6
RED_OUTB_5
RED_OUTB_4
DOBVDD3V
RED_OUTB_3
RED_OUTB_2
RED_OUTB_1
RED_OUTB_0
DOBVSS
GRN_OUTB_7
GRN_OUTB_6
GRN_OUTB_5
GRN_OUTB_4
DOBVDD3V
GRN_OUTB_3
GRN_OUTB_2
GRN_OUTB_1
GRN_OUTB_0
GRN_INB_4/HCLK
CZ1
39nF
CP1
150pF
G
1
CFG[1:0]
0 0 -> I2C
0 1 -> SPI
1 0 ->
6-WIRE
CFG[3:2]
R
V
3
2
INV1->D-HSYNC
CPH1->D-SHCLK2
POL->D-VSYNC
RLS->D-DE2
修改
4_B