Specifications

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INFF
GBUFx
PIO
Global
Buffer
Figure 53. PIO setup to input flip-flop before Global Buffer clock.
Speed Grade -25 -40
Description Symbol Device Min Min
Units
ZE502 7.0 5.5 ns
ZE505 7.0 5.5 ns
ZE512 7.0 5.5 ns
Set-Up: Delayed Input
Data set-up time before active clock edge to input
flip-flop or latch using a Global Buffer as clock, de-
layed input path.
T
GPSU
ZE520
7.0 5.5 ns
ZE502 0 0 ns
ZE505 0 0 ns
ZE512 0 0 ns
Set-Up: No Delayed Input
Data set-up time before active clock edge to input
flip-flop or latch using a Global Buffer as clock, no
delayed input path.
T
GPSN
ZE520 0 0 ns
ZE502 0 0 ns
ZE505 0 0 ns
ZE512 0 0 ns
Hold: Delayed Input
Data hold time after active clock edge to input flip-
flop or latch a Global Buffer as clock, delayed input
path.
T
GPHT
ZE520 0 0 ns
ZE502 3.5 3.0 ns
ZE505 3.5 3.0 ns
ZE512 3.5 3.0 ns
Hold: No Delayed Input
Data hold time after active clock edge to input flip-
flop or latch a Global Buffer as clock, delayed input
path.
T
GPHN
ZE520 3.5 3.0 ns
Preliminary
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The Memory Interface Unit on the ZE5 has user-defined control timing. Various control registers define
the setup, strobe width, and hold time for output-enable, write-enable, and chip-enable signals. These
registers are configured from within the FastChip development system.
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A[17:0]
D[7:0]
CE-
WE-
OE-
External
Byte-wide
Memory
Triscend E5
BCLK
Figure 54. Memory Interface Unit.