Specifications
97 www.zylogic.com.cn
Speed Grade All -25 -40
Description Symbol Device Min [1] Max Max
Units
ZE502 2.0 24.0 17.5 ns
ZE505 2.0 24.0 17.5 ns
ZE512 2.0 24.0 17.5 ns
Bus Clock Input (BCLK/XTAL) pad to output
delay using output flip-flop.
T
BPCO
ZE520
2.0 24.0 17.5 ns
Preliminary
Note 1:
Not tested. Guaranteed by design.
B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
k
I
I
n
n
p
p
u
u
t
t
t
t
o
o
O
O
u
u
t
t
p
p
u
u
t
t
E
E
n
n
a
a
b
b
l
l
e
e
D
D
e
e
l
l
a
a
y
y
OEFF
BusClock
BCLK/XTAL
PIO
35 pF
12 mA
Figure 49. Bus Clock to Output from output flip-flop, 12 mA driver.
Speed Grade All -25 -40
Description Symbol Device Min [1] Max Max
Units
ZE502 2.0 20.0 15.0 ns
ZE505 2.0 20.0 15.0 ns
ZE512 2.0 20.0 15.0 ns
Bus Clock Input (BCLK/XTAL) pad to output
valid using output-enable flip-flop.
T
BPEO
ZE520
2.0 20.0 15.0 ns
ZE502 2.0 32.0 22.0 ns
ZE505 2.0 32.0 22.0 ns
ZE512 2.0 32.0 22.0 ns
Bus Clock Input (BCLK/XTAL) pad to output
high-impedance (hi-Z) using output-enable
flip-flop.
T
BPEZ
ZE520
2.0 32.0 22.0 ns
Preliminary
Note 1:
Not tested. Guaranteed by design.
B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
k
,
,
I
I
n
n
p
p
u
u
t
t
S
S
e
e
t
t
-
-
U
U
p
p
a
a
n
n
d
d
H
H
o
o
l
l
d
d
INFF
BusClock
BCLK/XTAL
PIO
Figure 50. PIO setup to input flip-flop before Bus Clock.
Speed Grade -25 -40
Description Symbol Device Min Min
Units
ZE502 4.5 6.0 ns
ZE505 4.5 6.0 ns
ZE512 4.5 6.0 ns
Set-Up: Delayed Input
Data set-up time before active clock edge to input
flip-flop or latch using the Bus Clock Input as clock,
delayed input path.
T
BPSU
ZE520 4.5 6.0 ns
ZE502 0 0 ns
ZE505 0 0 ns
ZE512 0 0 ns
Set-Up: No Delayed Input
Data set-up time before active clock edge to input
flip-flop or latch using the Bus Clock Input as clock,
no delayed input path.
T
BPSN
ZE520 0 0 ns
ZE502 0 0 ns
ZE505 0 0 ns
ZE512 0 0 ns
Hold: Delayed Input
Data hold time after active clock edge to input flip-
flop or latch using the Bus Clock Input as clock,
delayed input path.
T
BPHT
ZE520 0 0 ns
Set-Up: No Dela
y
ed Input
T
BPHN
ZE502 4.5 6.0 ns