Specifications
Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 96
J
J
T
T
A
A
G
G
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m
m
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h
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t
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s
TCK
TMS
TDI
TDO
T
JBUS
T
JCH
T
JCL
T
JMSU
T
JDSU
T
JCKO
T
JMH
T
JDH
T
JBSN
Figure 47. JTAG timing diagram.
J
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T
A
A
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G
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i
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m
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C
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h
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Final Final
Speed Grade -25 -40
Description Symbol Fig. Device Min Max Min Max
Units
TCK frequency, boundary scan F
JBSN
1 All 0 10.0 0 10.0 MHz
TCK boundary scan cycle time T
JBSN
1 All 100
∞
100
∞
ns
TCK frequency, bus access F
JBUS
1 All 0 25.0 0 40.0 MHz
TCK bus access cycle time T
JBUS
1 All 40.0
∞
25.0
∞
ns
TCK High time T
JCH
1 All 11.0 11.0 ns
TCK Low time T
JCL
1 All 11.0 11.0 ns
TCK rise time T
JCRT
1 All 5.0 5.0 ns
TCK fall time T
JCFT
1 All 5.0 5.0 ns
TDI setup time before TCK rising
edge
T
JDSU
1 All 5.0 5.0 ns
TDI hold time after TCK rising edge T
JDH
1 All 2.0 2.0 ns
TMS setup time before TCK rising
edge
T
JMSU
1 All 5.0 5.0 ns
TMS hold time after TCK rising
edge
T
JMH
1 All 2.0 2.0 ns
TDO valid after TCK falling edge T
JCKO
1 All 1.0 15.7 1.0 11.5 ns
Final Final
P
P
i
i
n
n
-
-
t
t
o
o
-
-
P
P
i
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n
G
G
u
u
a
a
r
r
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t
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d
d
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m
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S
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p
p
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s
All Zylogic devices are 100% functionally tested. These parameters are modeled after the testing meth-
ods described by MIL-M-38510/605. Pin-to-pin timing parameters are derived by measuring external and
internal test patterns. The values listed below are representative for worst-case pin locations and clock
loading. Actual values may depend on application-specific use. FastChip reports specific, worst-case
guaranteed values in the Timing Analysis section of the project report.
All timing values shown assume worst-case operating conditions, including process technology, power
supply voltage, and junction temperature.
B
B
u
u
s
s
C
C
l
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o
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c
k
k
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O
O
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p
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D
D
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l
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OUTFF
BusClock
BCLK/XTAL
PIO
35 pF12 mA
Figure 48. Bus Clock to Output from output flip-flop, 12 mA driver.
批注 [SKK3]: SPICE
批注 [SKK4]: Real number
was 3.0 for setup, 1.0 for
hold. Adding padding to
allow for loading plus this
shouldn’t be an application
problem.