Specifications

95 www.zylogic.com.cn
Note 7:
Capacitance and inductance is sample-tested only.
Zylogic ZE5 Switching Characteristic Guidelines
All Zylogic devices are 100% functionally tested. These parameters are modeled after the testing meth-
ods described by MIL-M-38510/605. The values listed below are representative, guideline values ex-
tracted from measured internal test patterns. Actual values may depend on application-specific use. The
FastChip development system reports specific, worst-case guaranteed values in the Timing
Analysis section of the project report.
All timing values shown assume worst-case operating conditions, including process technology, power
supply voltage, and junction temperature.
P
P
r
r
o
o
d
d
u
u
c
c
t
t
S
S
t
t
a
a
t
t
u
u
s
s
D
D
e
e
f
f
i
i
n
n
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t
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o
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s
s
These specifications include a status designation as defined below.
Preview:
Initial estimates based on simulation or extrapolated data from other speed grades,
devices, families, or process technologies. These values are subject to change with-
out notice. These values are estimates and should not be used for production.
Preliminary:
Based on preliminary or partial device characterization. Though further changes are
not expected, these values are subject to change without notice. These values are
safe for producing prototypes but should not be used for high-volume production.
Final or
Unmarked:
Specifications are final. These specifications may be used for volume production.
Values cannot change without notice.
Guideline:
A worst-case value or a range of worst-case values based on example applications
under a variety of conditions. Actual worst-case values are reported for the specific
use within an application by the FastChip development system in the Timing Analysis
section of the project report. The value reported by FastChip may not match the val-
ues shown herein. The value reported by FastChip supercedes any value shown be-
low.
G
G
e
e
n
n
e
e
r
r
a
a
l
l
Z
Z
E
E
5
5
T
T
i
i
m
m
i
i
n
n
g
g
C
C
h
h
a
a
r
r
a
a
c
c
t
t
e
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r
r
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Final
Speed Grade All -25 -40
Description Symbol Device Min Max Max
Units
Bus Clock frequency F
BCLK
All 0 25.0 40.0 MHz
Bus Clock high time T
BCH
All 12.0 ns
Bs Clock low time T
BCL
All 12.0 ns
Bus Clock rise time T
BCRT
All 5.0 5.0 ns
Bus Clock fall time T
BCFT
All 5.0 5.0 ns
32 kHz crystal start-up time T
32STU
All 200.0 200.0 ms
2–24 MHz Crystal start-up time T
XSTU
All 5.0 5.0 ms
Internal ring oscillator frequency F
ROSC
All 5.0 20.0 20.0 MHz
RST- pulse width T
RSTW
All 20.0 ns
Power-on reset delay after power valid T
RSTW
All 13 52 52 µs
Final
批注 [SKK1]: Needs SPICE
simulation
批注 [SKK2]: Assuming 260
clock cycles using internal
ring oscillator.