Specifications

9 www.zylogic.com.cn
CRC signature can be compared with the expected
value.
The CRC logic uses a CRC-CCITT 16-bit divisor
polynomial, as shown in the equation below. The
algorithm is capable of detecting any one, two or
an even number of bits in error as well as a large
number of burst errors.
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16
+ X
12
+ X
5
+ 1
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The DMA controller can generate interrupts upon
the following three events.
Transfer terminal count: This event is generated
when a block transfer is complete (when the trans-
fer counter reaches its terminal count of 0).
Transfer Initialization: This event is generated
upon the first request of block transfer if the INIT
bit is set.
Pending Request Overflow: This event is gener-
ated when the pending request counter overflows,
indicating that the DMA controller cannot keep up
with the number of incoming requests.
The status of these events is recorded in the inter-
rupt status register, independent of their corre-
sponding interrupt-enable bits. The status bits are
reset by software by writing a one into them. Writ-
ing a zero does not affect the state of any status
bits. Some of the status bits are also cleared by
some hardware action (refer to "DMA Interrupt
Register").
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Each channel has a set of 21 bytes of control and
status registers. Some registers are used to pro-
gram a specific DMA channel or to query its status.
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This set of registers defines the start address of
the DMA transfer. The register values are loaded
into the Address Counter at the beginning of a
transfer.
The DMA controller operates on 32-bit physical
address values, whereas the microcontroller oper-
ates on 16-bit logical address values. The physical
address for a memory location is typically assigned
automatically by the Zylogic FastChip development
system and included in a header file for the user.
The values are read/writeable.
Channel 0:
DMA Source Address Channel 0 (A[7:0])
A7 A6 A5 A4 A3 A2 A1 A0
76543210
Mnemonic: DMASADR0_0 Address: FF20h
DMA Source Address Channel 0 (A[15:8])
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMASADR0_1 Address: FF21h
DMA Source Address Channel 0 (A[23:16])
A23 A22A21A20A19A18A17A16
76543210
Mnemonic: DMASADR0_2 Address: FF22h
DMA Source Address Channel 0 (A[31:24])
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: DMASADR0_3 Address: FF23h
Channel 1:
DMA Source Address Channel 1 (A[7:0])
A7 A6 A5 A4 A3 A2 A1 A0
76543210
Mnemonic: DMASADR1_0 Address: FF34h
DMA Source Address Channel 1 (A[15:8])
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMASADR1_1 Address: FF35h
DMA Source Address Channel 1 (A[23:16])
A23 A22A21A20A19A18A17A16
76543210
Mnemonic: DMASADR1_2 Address: FF36h
DMA Source Address Channel 1 (A[31:24])
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: DMASADR1_3 Address: FF37h
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This field specifies the byte length of the DMA
transfer. The actual value is the number of
bytes transfer minus one. This value is loaded
into the transfer counter before the transfer starts.
The values are read/writeable.
Channel 0:
DMA Transfer Count Channel 0 (CNT[7:0])
CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
76543210
Mnemonic: DMASCNT0_0 Address: FF24h