Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 8
can be combined to form more complex and pow-
erful operations.
S
S
i
i
n
n
g
g
l
l
e
e
T
T
r
r
a
a
n
n
s
s
f
f
e
e
r
r
M
M
o
o
d
d
e
e
In this mode, the DMA initiates a single byte trans-
fer for each request. If the requests are asserted
during every cycle, then the DMA controller at-
tempts to service the requests as fast as it can.
The DMA services requests until the transfer count
reaches zero. At that point, the transfer is com-
pleted. This is the default mode.
B
B
l
l
o
o
c
c
k
k
T
T
r
r
a
a
n
n
s
s
f
f
e
e
r
r
M
M
o
o
d
d
e
e
In this mode, a single request initiates a transfer of
an entire block of data. Upon receiving the request,
the DMA controller starts transferring data until the
transfer count reaches zero. If a request is re-
ceived at any time during the block transfer, the
request is recorded in the Pending Requests
Counter. The new request is serviced at the end
of the current block transfer.
S
S
o
o
f
f
t
t
w
w
a
a
r
r
e
e
R
R
e
e
q
q
u
u
e
e
s
s
t
t
When this mode is active, the DMA controller re-
sponds to a DMA request initiated from software.
Setting the SFTREQ bit in the DMA channel con-
trol register enables this mode. Software can then
request a DMA transfer. Software requests that
cannot currently be served are recorded in the
pending request counter. A software request is
cleared by hardware on the cycle following the set
operation. If the software request is set while the
DMA channel is disabled, then the request is ig-
nored.
S
S
i
i
n
n
g
g
l
l
e
e
I
I
n
n
i
i
t
t
i
i
a
a
l
l
i
i
z
z
a
a
t
t
i
i
o
o
n
n
Setting the INIT bit initializes a transfer. Upon re-
ceiving the first request, the INIT bit is reset by
hardware and the single, software or block transfer
continues until the transfer count reaches zero. At
that point, the DMA controller waits for a new ini-
tialization command.
C
C
o
o
n
n
t
t
i
i
n
n
u
u
o
o
u
u
s
s
A
A
u
u
t
t
o
o
-
-
I
I
n
n
i
i
t
t
i
i
a
a
l
l
i
i
z
z
a
a
t
t
i
i
o
o
n
n
Setting the CONT initiates a transfer similar to the
INIT bit, but upon completion of the current transfer,
the DMA controller automatically reinitializes as if
the INIT bit were set again. Automatic refresh of
some external display is one potential application
of this mode.
M
M
e
e
m
m
o
o
r
r
y
y
-
-
t
t
o
o
-
-
M
M
e
e
m
m
o
o
r
r
y
y
T
T
r
r
a
a
n
n
s
s
f
f
e
e
r
r
By pairing the channels together, the DMA control-
ler supports memory-to-memory transfers. The
channel that reads the data from memory, is the
master, and the other channel, which writes the
data back into memory, is the slave. Setting the
PAIR bit in the control register of both channels
enables this mode. Transfers are initiated using
the master's control register. However, the slave
channel must be enabled and its transfer parame-
ters set correctly.
L
L
i
i
n
n
k
k
e
e
d
d
t
t
r
r
a
a
n
n
s
s
f
f
e
e
r
r
s
s
Linked transfers are possible using a single-
initialization, software block transfer. The parame-
ters of the first block transfers are programmed
into the appropriate control registers and the trans-
fer is initiated through the INIT bit and the
SFTREQ bit. Once the INIT bit is cleared by hard-
ware—meaning the DMA channel has initiated the
transfer—software loads the address and transfer
count parameters of the next block of data. After
loading the parameters, software sets the INIT and
SFTREQ bits. Upon completion of the first block
transfer, the DMA channel loads the new parame-
ters and initiates the new transfer. Software re-
peats the previous steps until it reaches the end of
the linked list.
B
B
u
u
s
s
A
A
d
d
d
d
r
r
e
e
s
s
s
s
G
G
e
e
n
n
e
e
r
r
a
a
t
t
i
i
o
o
n
n
Each DMA channel generates a memory address
for every request. The first address of a block
transfer is the starting address, held in starting ad-
dress control register. This address value is then
loaded into the current address counter upon the
first request of a block transfer. Once the address
is broadcast to memory, it is updated for the next
request. The addressing option is configured
through two of the DMA channel's control register
bits, as shown in Table 2.
For debug purposes, the current address of a
block transfer as well as the current count are visi-
ble to software.
D
D
a
a
t
t
a
a
F
F
I
I
F
F
O
O
The data FIFO serves as a temporary buffer be-
tween the requesting I/O device and memory. Be-
cause of the CSI bus structure and the multi-
master handshaking, four locations are required.
C
C
R
R
C
C
F
F
e
e
a
a
t
t
u
u
r
r
e
e
A cyclic redundancy check (CRC) can be per-
formed on a single DMA stream. The CRC logic
monitors the Data Read bus as it enters the DMA's
FIFOs. The CRC logic is shared between the two
DMA channels and is enabled for either one of the
channels by setting the CRC_EN bit in the corre-
sponding DMA channel control register. A 0-to-1
transition on CRC_EN resets the CRC shift-
register to zero. Once enabled, the CRC logic is
activated any time a byte of data is written into a
FIFO. Once a transfer is completed, the output of
the CRC register can be read by software, and the