Specifications

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Pin Name Pin Description Parallel Serial Slave
VCC
Supply voltage for internal logic functions, separate from
I/O. Connect to a +3.3 volt supply. All must be con-
nected and each must be decoupled with a 0.01 to 0.1
µF capacitor to ground.
I I I
VCCIO
Supply voltage for I/O functions, separate from internal
logic. Connect to a +3.3 volt supply. All must be con-
nected and each must be decoupled with a 0.01 to 0.1
µF capacitor to ground.
I I I
VSYS
External 'system voltage-good' indicator input. Indicates
when external devices have sufficient operating voltage.
In most applications, connect VSYS to VCCIO supply
source or to a "Power Good" output from the system
power supply. If VSYS is High during initialization and
no valid configuration is found, the CSoC device auto-
matically powers down to conserve power. If VSYS is
Low, the CSoC device attempts to initialize itself until it
finds valid initialization data. This pin must be con-
nected. Do not allow it to float.
I I I
WE-/SEN-
Active-Low write-enable signal typically used to program
external FLASH-based devices. An output when the
ZE5 accesses external memory during initialization in
parallel or serial modes. An input while in slave mode.
O O I
XTALIN
The input from the external crystal into the internal crys-
tal oscillator amplifier. Connect to one side of the exter-
nal crystal or ceramic resonator. Leave unconnected if
not using an external crystal or resonator.
I I I
Pinout Diagrams and Tables
A
A
v
v
a
a
i
i
l
l
a
a
b
b
l
l
e
e
P
P
a
a
c
c
k
k
a
a
g
g
e
e
s
s
a
a
n
n
d
d
P
P
a
a
c
c
k
k
a
a
g
g
e
e
C
C
o
o
d
d
e
e
s
s
Each Zylogic ZE5 family member is available in
different packages. Each ordering code contains a
letter defining the package style, as shown in
Table 44.
Table 44. Package Codes.
Package
Code
Package
Type
L 128-pin PQFP
Q 208-pin PQFP
B 484-ball BGA
F
F
o
o
o
o
t
t
p
p
r
r
i
i
n
n
t
t
-
-
C
C
o
o
m
m
p
p
a
a
t
t
i
i
b
b
i
i
l
l
i
i
t
t
y
y
Each Zylogic ZE5 configurable system-on-chip is
designed to be footprint compatibly with other ZE5
family members available in the same package,
providing additional design and manufacturing
flexibility. A designer can easily select a larger or
more cost-effective ZE5 device that fits a pre-
existing printed circuit board (PCB) design.
Though the Zylogic ZE5 and A7 families are avail-
able in similar package options, the ZE5 and A7
families are not pin compatible with one another.
A
A
v
v
a
a
i
i
l
l
a
a
b
b
l
l
e
e
P
P
I
I
O
O
s
s
b
b
y
y
P
P
a
a
c
c
k
k
a
a
g
g
e
e
The number of user-configurable PIO pins de-
pends on the base device type and the package in
which it is packaged. Table 45 shows the avail-
able PIOs by package style. Two values are indi-
cated for each device type, one for parallel mode
and one for serial mode configuration. Both cases
assume that the upper address bits, A[31:18] are
used as PIOs, which is the default case.
Table 45. Available PIOs by Package
Device Mode LQ128 PQ208 BG484
Parallel 52
ZE502
Serial 76
Parallel 60 100
ZE505
Serial 84 124
Parallel 60 126
ZE512
Serial 84 150
Parallel 126 228
ZE520
Serial 150 252
Parallel 126 292
ZE532
Serial
150 316