Specifications

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Pin Name Pin Description Parallel Serial Slave
GNDIO
Ground connection for I/O functions; connect to ground
for internal logic. All must be connected.
I I I
N.C. No connect. There is no function on this pin. N.C. N.C. N.C.
OE-/SRST
Active-Low output-enable signal. An output when the
configurable system-on-chip accesses external memory
during initialization in parallel or serial modes. An input
while in slave mode.
O O I
PIO
General-purpose input, output, or bi-directional signal pin
after initialization is complete. Before initialization is
complete, these pins have internal high-impedance pull-
up resistors that pull the signal pin to a High logic level.
I (pull-up) I (pull-up) I (pull-up)
PIO/A18
PIO/A19
PIO/A20
PIO/A21
PIO/A22
PIO/A23
PIO/A24
PIO/A25
PIO/A26
PIO/A27
PIO/A28
PIO/A29
PIO/A30
Typically, a general-purpose input, output, or bi-
directional signal pin after initialization is complete. Be-
fore initialization is complete, this pin has an internal
high-impedance pull-up resistor that pulls the signal pin
to a High logic level. Also used in multi-chip mode to
expand the upper address bits for external accesses.
I (pull-up) I (pull-up) I (pull-up)
PIO/GBUF5
PIO/GBUF4
PIO/GBUF3
PIO/GBUF2
PIO/GBUF1
PIO/GBUF0
Global buffer input. Typically, a general-purpose input,
output, or bi-directional signal pin after initialization is
complete. Before initialization is complete, this pin has
an internal high-impedance pull-up resistor that pull the
signal pin to a High
I (pull-up) I (pull-up) I (pull-up)
PIO/XDONE
External data transfer done signal. Typically, a general-
purpose input, output, or bi-directional signal pin after
initialization is complete. Before initialization is com-
plete, this pin has an internal high-impedance pull-up
resistor that pulls the signal pin to a High logic level.
Also used in multi-chip mode to for inter-device transfer
handshaking.
I (pull-up) I (pull-up) I (pull-up)
PMOD/PIO/
A31
Tied Low during initialization to indicate serial mode.
Left floating or pulled High during initialization for parallel
mode. Also a potential general-purpose input, output, or
bi-directional signal pin after initialization is complete but
with the restrictions described above. Before initializa-
tion is complete, this pin has an internal high-impedance
pull-up resistor that pulls the signal pin to a High logic
level. Also used in multi-chip mode to expand the upper
address bits for external accesses.
I (pull-up) I (pull-up) I (pull-up)
RST- Device reset input. Active Low. I I I
SLAVE-
Slave mode input. Active Low. Tie High for most appli-
cations indicating that the CSoC device initializes itself
from an external PROM, either parallel or serial. Tie
Low if another processor initializes the CSoC device via
the MIU interface. This pin must be connected. Do not
allow it to float.
I I I
TCK JTAG Test Clock input. Tie High if unused. I I I
TDI JTAG Test Data Input. Tie High if unused. I I I
TDO JTAG Test Data Output. O O O