Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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Pin Description
Table 43 describes the pins available on an ZE5 configurable system-on-chip device. The directionality
of each pin is described for parallel, serial, and slave mode initialization. O=output. I=input. I (pull-
up)=input pin with soft pull-up during initialization—pin appears to float High.
Table 43. Pins available on an ZE5 configurable system-on-chip and their function.
Pin Name Pin Description Parallel Serial Slave
A0/SCLK
Address bus bit 0 from the MIU in parallel mode.
Serial clock output to serial PROM in serial mode.
In slave mode, this pin has an internal high-impedance
pull-up resistor that is active until initialization is com-
plete.
O O
I (pull-up)
A17/PIO
A16/PIO
A15/PIO
A14/PIO
A13/PIO
A12/PIO
A11/PIO
A10/PIO
A9/PIO
A8/PIO
A7/PIO
A6/PIO
A5/PIO
A4/PIO
A3/PIO
A2/PIO
A1/PIO
Address bus bit in parallel mode.
In other modes, this pin may be used as a PIO. Until
initialization is complete, this pin has an internal high-
impedance pull-up resistor.
O
I (pull-up) I (pull-up)
BCLK/XTAL
Bus clock input from an external clock source or the out-
put from the internal crystal oscillator amplifier. Connect
to one side of the external crystal or ceramic resonator
or to an external clock source.
O O O
CE-
Active-Low chip-enable signal. An output when the con-
figurable system-on-chip accesses external memory dur-
ing initialization in either parallel or serial modes.
An input while in slave mode.
O O I
D0/SDIN
Data bus bit 0 in parallel mode.
Serial data input (SDIN) in serial mode.
In slave mode, this pin has an internal high-impedance
pull-up resistor that is active until initialization is com-
plete.
I I
I (pull-up)
D7/PIO
D6/PIO
D5/PIO
D4/PIO
D3/PIO
D2/PIO
D1/PIO
Data bus bit in parallel mode.
In other modes, this pin may be used as a PIO. Until
initialization is complete, this pin has an internal high-
impedance pull-up resistor.
I
I (pull-up) I (pull-up)
GND
Ground connection for internal logic; connect to ground
for I/O functions. All must be connected.
I I I