Specifications

75 www.zylogic.com.cn
 Added information about pin directionality during
initialization to Pin Description.
 Added additional information on the VSYS and
SLAVE- pins to Pin Description.
 Added information on using TH1 to control the baud
rate for the serial port. See Timer 1 MSB.
 Added information on using RCAP2H and RCAP2L
to control the baud rate for the serial port. See
Timer 2 Capture LSB and Timer 2 Capture MSB.
 Added details to 5-volt tolerant PIO support. See 5-
Volt Tolerant I/Os.
 Updated PIO drawing to reflect proper location of
inversion multiplexer on output and output-enable
signal paths, as shown in Figure 27.
 Added additional detail on how the CSI bus re-
sources operate. See Configurable System Inter-
connect (CSI) Bus.
 Added information on how a Selector can address an
external peripheral connected to the MIU bus. See
Figure 13 and External Memory Request Mode.
 Added debugging support requirements. See
Debugging Support System Requirements.
 Added phrase about using the internal feedback re-
sistor when using the internal crystal oscillator ampli-
fied. See System clock select (BCLK).
 Corrected the direction of the inverting buffer for the
crystal oscillator amplified in Figure 44.
 The largest ball-grid array packaged changed to a
484-ball BGA package. Affects Table 44, Table 45,
Ordering Information, and the previous BGA pinout
diagrams and pinout tables were removed from this
version.
 Renamed sideband signals INT0, INT1 to INTR0,
INTR1 to be consistent with FastChip naming.