Specifications
Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 74
an interrupt service routine (ISR) for the corre-
sponding external interrupt. After the interrupt ser-
vice routine is completed, the program execution
returns to the instruction after the one that put the
device into Power Down mode and continues from
there.
Upon receiving an interrupt, the PCON SFR power
down bit (PDBIT) is asynchronously reset to “0”. In
turn, it re-enables all the circuits that were selected
for power down blocking. Again, if the crystal os-
cillator was blocked during power down, the inter-
rupt routine must switch back from the internal ring
oscillator to the crystal oscillator.
Glossary
CSoC - Configurable System-on-Chip. A configur-
able device containing a dedicated processor, con-
figurable logic, on-chip RAM, and a dedicated in-
ternal bus.
CRU - Configuration Register Unit. Registers that
define special functions on the Zylogic ZE5 device.
CSL - Configurable System Logic. The peripheral
configurable logic matrix providing user-
programmable functions to the microcontroller and
its peripherals.
CSI - Configurable System Interconnect. The on-
chip bus that bridges the Configurable System
Logic (CSL) matrix, the 8032 "Turbo" microcontrol-
ler, the dedicated peripherals, and the Memory
Interface Unit (MIU).
DMA - Direct Memory Access. A controller that
offloads memory and I/O transfers from the micro-
controller.
JTAG - Joint Test Action Group. A general name
given to the four-wire serial interface described in
IEEE 1149.1.
MCU - Microcontroller Unit. The 8032 "Turbo" mi-
crocontroller embedded within the Zylogic ZE5
configurable system-on-chip.
MIU - Memory Interface Unit. Connects the micro-
controller, its peripherals, and the internal system
bus to external memory resources.
PIO - Programmable Input/Output.
SFR - Special Function Register. An 8032-based
term for registers that control the microcontrollers
peripheral functions.
Life Support Policy
Zylogic's products are not authorized for use as
critical components in life support devices or sys-
tems unless a specific written agreement pertain-
ing to such intended use is executed between the
manufacturer and the President of Zylogic.
1. Life support devices or systems are devices
which (a) are intended for surgical implant into
the body or (b) support or sustain life and
whose failure to perform, when properly used
in accordance with instructions for use pro-
vided in the labeling, can be reasonably ex-
pected to result in significant injury to the user.
2. Critical component in any component of a life
support device or system whose failure to per-
form can be reasonably expected to cause the
failure of the life support device system, or af-
fect its safety or effectiveness.
Revision List
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Added Zylogic ZE5 Switching Characteristic
Guidelines section.
Removed 208-pin PQFP as a package option for the
ZE502. Affects Table 45, 208-pin Plastic Quad Flat
Pack, top view (Package Code=Q) drawing, 208-pin
PQFP (Package Code=Q) Package Pinout Tables,
and 208-pin PQFP Pins by Type.
Added information on 484-ball BGA package.
Added notes 2 through 7 to
Electrical and Timing
Characteristics
page.
Added TTL output current specifications to
Recommended Operating Conditions/DC Charac-
teristics.
Added
128-pin LQFP and 208-pin PQFP Land
Pattern Dimensions
.
Provided additional details on output drive current.
See Table 14.
Added additional description to VSYS pin.
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Corrected the address for the MISC register in text.
The correct location is 0xfe81.
Corrected a typo in the zip code for Zylogic's mailing
address.
Updated hyper-links to Zylogic sales office and inter-
national representatives.
Updated the E-mail address for Zylogic.
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Updated specification for ZE512 device to reflect
SRAM size change from 16K bytes to 32K bytes.
Change affects Table 1, Table 20, chart under
Ordering Information, and the 128-pin and 208-pin
package pinout drawings.
Corrected polarity of input signals during power-down.
Correct value is Low. Affects description of PIO bit in
the Power Down Select register and Input Options
for the PIO low-power mode.
Added a register description for the 8032's B register
SFR. See B Register.