Specifications

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crystal and set the MIU read timing parameters to
the pre-power-down values.
Table 42 summarizes the sequence for entering
and exiting power down mode, when turning off the
crystal oscillator during power-down mode. The
method used depends on the crystal frequency.
With the crystal shut off, the device wakes from
power-down mode using the internal ring oscillator.
The sequences in Table 42 represent the cases
where the crystal is faster and slower than the in-
ternal ring oscillator.
The registers accessed in Table 42 are MIUCTRL
and MISC. MIUCTRL controls the MIU timing and
MISC contains the clock select bit. These regis-
ters are configuration register (CRU) bits. The
CRU block size must be set to 4K bytes in order to
enable access to these registers by clearing the
DMAP3_CTL.0 bit.
Table 42. MIU Timing Considerations for
Powering Down the Crystal Oscillator.
XTAL
Freq.
Power Down
Sequence
Exit power
down sequence
< 20MHz
Add more cycles
to MIU read tim-
ing in order to
work with a
20MHz clock
Set power down
mode.
Wait desired time
for crystal to stabi-
lize
Switch clock
source to external
crystal
Optimize MIU read
timing back to
XTAL frequency
value.
> 20MHz
Set power down
mode
Wait desired time
for crystal to stabi-
lize
Optimize MIU read
timing back to
XTAL frequency
value.
Switch clock
source to external
crystal
The MIUCTRL register (external data default loca-
tion FE33h) is described in the MIU section.
The MISC register is located at the external default
address location FE81h. The clock select bit is in
bit location 0. When cleared, the default value, the
internal ring oscillator becomes the bus clock
source. If set, then the external clock oscillator
drives the bus clock.
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E
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The Zylogic ZE5 configurable system-on-chip exits
power down mode either from a reset or by assert-
ing either INTR0 or INTR1 sideband signal config-
ured as a level-sensitive interrupt. An external re-
set causes the device to exit the Power down state.
The Low on RST- pin terminates the Power Down
mode, and restarts the clock. In the Power down
mode, all clocks are stopped, so the Watchdog
timer cannot be used to provide the reset to exit
Power down mode. The Power on/fail reset, how-
ever, provides reset if power falls below the thresh-
old level of VRST.
Three different events cause the device to exit
power down mode.
1. Apply a reset pulse on the RST- pin.
2. Assert the application-reset signal, RSTC.
3. Interrupt the MCU using one of the external
interrupt sideband signals, INTR0 or INTR1
and hold the signal for at least two machine
cycles.
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Applying a reset pulse on the external RST- pin
causes the Zylogic ZE5 to exit power-down mode.
When asserted, the RST- pulse resets the entire
system, including MCU and its PCON SFR. The
internal ring oscillator becomes the default system
clock source and the device begins the initializa-
tion process. The clock source selection for bus
clock happens during initialization. At the end of
initialization, the CPU begins executing the user’s
application program. This method of exiting power
down mode might be too slow for some applica-
tions.
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Another method to exit power down mode is to
assert the application reset sideband signal, RSTC,
from within the CSL matrix. The MCU re-starts
executing the application program from 0000h. If
the crystal oscillator was blocked during power
down, then default clock source is the internal os-
cillator. Before switching back to the crystal oscil-
lator, the user program must wait for the crystal
oscillator to stabilize.
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The ZE5 wakes from the Power Down mode by
asserting the INTR0 or INTR1 interrupt sideband
signals. The corresponding interrupt must be en-
abled, the global interrupt enable bit must be set
and the INTR0 and INTR1 sideband signals con-
figured in level-sensitive mode. If these conditions
are met, then asserting the external pin re-enables
the on-chip oscillator. The INTR0 or INTR1 side-
band signal should be asserted long enough for
the internal oscillator to start and stabilize. The
power down mode is finally exited when the exter-
nal interrupt is released. The device then executes