Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 72
After a reset condition, the program counter is re-
set to 0000h and all the SFRs are set to the reset
condition. Because the clock is already running,
there is no delay and execution starts immediately.
In the Idle mode, the Watchdog timer continues to
run, and if enabled, a time-out will cause a watch-
dog timer interrupt, which will wake up the device.
The software must reset the Watchdog timer in
order to preempt the reset, which will occur 512
clock periods after the time-out. When the MCU
exits from the Idle mode with a reset, the instruc-
tion following the one which put the device into Idle
mode is not executed.
P
P
o
o
w
w
e
e
r
r
-
-
D
D
o
o
w
w
n
n
M
M
o
o
d
d
e
e
The device is placed into power-down mode by
setting the PCON.1 bit. The instruction that sets
this bit is the last instruction executed before the
device goes into power-down mode. In power-
down mode, all clocks are optionally stopped and
internal functions optionally disabled. All activity is
completely stopped and the power consumption is
reduced to the lowest possible value.
The power down control logic optionally prevents
the global clock signals from toggling when the
MCU powers down. The PWDSEL defines the
system behavior when the system enters the
power down mode.
The MCU is powered down following the execution
of an instruction that set the PD flag inside its
PCON register. The MCU exits power down by a
reset pulse or by responding to an external inter-
rupt, as described later.
Prior to entering a power down state, the applica-
tion program configures PWDSEL with settings
that best fits the particular application.
P
P
o
o
w
w
e
e
r
r
D
D
o
o
w
w
n
n
S
S
e
e
l
l
e
e
c
c
t
t
- -PIOXTALOSCGBUF
CSL
BCLK
BCLK
76543210
Mnemonic: PWDSEL Address: FF62h
PIO, when set, signals all of the PIO pins when a
power-down event occurs. Within each PIO, user-
defined values configure the PIO to optionally
block inputs by driving a Low value. In addition,
the output driver is optionally three-stated, turning
on the weak-follower feature. The individual PIO
controls are loaded during device initialization.
XTAL, when set, blocks the external oscillator dur-
ing power down mode. BCLK is frozen in its High
state. Note that the memory interface unit (MIU)
must be set up correctly to properly exit power
down mode, as described later.
OSC, when set, shuts off the internal oscillator dur-
ing power down mode.
GBUF, when set, signals the six global buffers
when a power-down event occurs. Each global
buffer has individual control bits that define its be-
havior during a power down or breakpoint event.
CSL_BCLK, when set, blocks the bus clock into
the configurable system logic (CSL) matrix during
power-down mode.
BCLK, when set, blocks the bus clock during
power-down mode.
Power down mode is initiated by writing a “1” to the
power down bit in the microcontroller’s PCON SFR.
Depending on what portions of the device are se-
lected for shut down or blocking, the effect is im-
mediate. However, special attention is required
when exiting power down mode after shutting off
the crystal oscillator.
P
P
o
o
w
w
e
e
r
r
-
-
O
O
n
n
R
R
e
e
s
s
e
e
t
t
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- ------PORCT
76543210
Mnemonic: PORCTRL Address: FF63h
PORCT, when set, disables the Power-On Reset
(POR) circuitry during power-down mode. Clear-
ing this bit keeps the POR circuitry active.
Power down mode is initiated by writing a “1” to the
power down bit in the microcontroller’s PCON SFR.
S
S
h
h
u
u
t
t
t
t
i
i
n
n
g
g
D
D
o
o
w
w
n
n
t
t
h
h
e
e
C
C
r
r
y
y
s
s
t
t
a
a
l
l
O
O
s
s
c
c
i
i
l
l
l
l
a
a
t
t
o
o
r
r
If the external crystal is selected to drive the inter-
nal system clock (BCLK), it can be shut down dur-
ing power-down by setting the XTAL bit. However,
if the crystal oscillator is shut down, the device
automatically selects the internal ring oscillator as
the default clock source upon exiting power down
mode. Consequently, if the user program fetches
instructions via the MIU when leaving power
down—the usual case—potential timing problems
could occur if the frequency of the internal ring os-
cillator is greater than the frequency of the external
crystal. Before entering power down mode, the
user application code must properly configure the
MIU’s external memory timing with values that are
more conservative. See Table 42 for more details.
R
R
e
e
s
s
t
t
a
a
r
r
t
t
i
i
n
n
g
g
t
t
h
h
e
e
C
C
r
r
y
y
s
s
t
t
a
a
l
l
O
O
s
s
c
c
i
i
l
l
l
l
a
a
t
t
o
o
r
r
a
a
f
f
t
t
e
e
r
r
E
E
x
x
i
i
t
t
i
i
n
n
g
g
P
P
o
o
w
w
e
e
r
r
-
-
D
D
o
o
w
w
n
n
M
M
o
o
d
d
e
e
If the crystal oscillator is disabled during power
down, then the internal ring oscillator becomes the
clock source for the bus clock, BCLK.
Before switching back to the crystal oscillator, the
user program must wait for the crystal oscillator to
stabilize. This can be accomplished either by a
software timing loop or by using one of the MCU
timers. Once the necessary time has elapsed, the
user program must switch back to the external