Specifications

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SFR Name Reset Value
TCON 00000000b
TH0 00000000b
TH1 00000000b
TH2 00000000b
TL0 00000000b
TL1 00000000b
TL2 00000000b
TMOD 00000000b
Most of the SFRs and registers on the device are
cleared by reset. The Program Counter is forced
to 0000h and is held there as long as the reset
condition is applied. The reset state however does
not affect the on-chip RAM. The data in the RAM
is preserved during the reset. However, the stack
pointer is reset to 07h, and therefore the stack con-
tents are lost. However, the RAM contents will be
lost if the Vcc falls below approximately 2V, as this
is the minimum voltage level required for the RAM
to operate normally. Therefore, after a first-time
power on reset, the RAM contents are indetermi-
nate. During a power fail condition, if the power
falls below 2V, the RAM contents are lost. After a
power on/fail reset, POR = 1, the RAM contents
should be assumed lost.
When reset, most SFRs are cleared, as shown in
Table 40. Interrupts and Timers are disabled.
The Watchdog timer is disabled by a Power-On
Reset (POR). The WDCON SFR bits are set or
cleared in reset condition depending on the source
of the reset, as shown in Table 41.
Table 41. Watchdog Timer Reset Values.
External
Reset
Watchdog
Reset
Power-on
Reset
WDCON
1x0x0xx0b 1x0x01x0b 11000000b
An 'x' indicates that the reset does not change the
bit. The POR bit WDCON.6 is set only by the
power on reset. The PFI bit WDCON.4 is set when
the power fail condition occurs. However a power-
on reset clears this bit if Vcc> Vpfw following the
crystal start-up time. The WTRF bit WDCON.2 is
set when the Watchdog timer causes a reset. A
power-on reset also clears this bit. The EWT bit
WDCON.1 is cleared by power-on resets. This dis-
ables the Watchdog timer resets. A watchdog or
external reset does not affect the EWT bit.
Power Management
The Zylogic ZE5 configurable system-on-chip has
several features that reduce power consumption,
including two power saving modes, Power-Down
and Idle. A power-on/power-fail reset guarantees
proper start-up or restart operation.
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The Zylogic ZE5 configurable system-on-chip has
a built-in power-on reset system. This ensures
that if the power levels are below the VRST level,
the device is forced into the reset state. When
power is turned on—such as during a cold reset—
the device is reset automatically and remains so as
long as VCC is less that VRST. Similarly, when
power falls below VRST, the device is automati-
cally reset. This eliminates the need for any exter-
nal reset circuitry.
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The Zylogic ZE5 has two power saving modes of
operation, the Power Down mode and the Idle
mode. These two modes are possible because the
ZE5 is implemented in fully static CMOS logic.
This permits the device to reduce the clock speed
to DC. In the most aggressive power down state,
where subsystems are properly shut down or
blocked, the overall current can be reduced to a
typical value of less than 50 µA.
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The Idle mode is primarily provided for compatibil-
ity with the original 8032 microcontroller. The de-
vice is placed in Idle mode by setting the IDL bit
(PCON.0). The instruction that sets the idle bit is
the last instruction executed before the device
goes into Idle mode.
In the Idle mode, the MCU clock is disabled. How-
ever, the interrupt controllers, timers, watchdog
timer, and serial port continue to operate. Idle
mode freezes the MCU state including the Pro-
gram Counter, the Stack Pointer, the Program
Status Word, and the Accumulator. The other reg-
isters retain their contents.
There are two ways to exit Idle mode. Because
the interrupt controller remains active, asserting
any enabled interrupt wakes up the processor.
This automatically clears the Idle bit, terminates
the Idle mode, and executes the appropriate inter-
rupt service routine (ISR). After the ISR, the pro-
gram continues to execute from the instruction fol-
lowing the instruction that placed device into Idle
mode.
An alternate method to exit the Idle mode is by
forcing a reset condition. The device is reset by
either applying a Low on the external RST- pin, a
Power on/fail reset condition, a Watchdog timer
reset, or asserting an application reset using the
RSTC sideband signal. Some reset conditions
cause the Zylogic ZE5 device to re-initialize before
re-starting code execution from 0000h. See the
"System Initialization" section for more informa-
tion.