Specifications

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itself with a particular channel through a DMA con-
trol register (DMACTRL), which contains a request
and acknowledge signal pair. The two DMA chan-
nels can also be paired to perform memory-to-
memory operations.
The main features of the DMA controller unit are:
 Two independent channels for device or mem-
ory transfers
 Transfer rates up to 40 Mbytes/sec
 Auto-initialization of channels
 Programmable transfer parameters
 Multiple addressing modes
 Interrupt capabilities
 Memory-to-memory transfers capabilities
 Block transfers
 Software-initiated DMA requests
 Four-byte FIFO
 Asynchronous request/acknowledge handshake
 CRC on DMA data stream
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The DMA unit is composed of two channels as
shown in Figure 4. A set of parameters defines the
operation for a specific DMA channel, including the
memory starting address and starting transfer
count, the direction of the transfer, and a variety of
other transfer characteristics. Each channel has
its own register set. The control logic block con-
tains the address counter, the current transfer
count, the pending requests counter and channel
control logic. The data FIFO serves as a tempo-
rary buffer between the I/O device and memory.
The CSI bus arbiter treats each channel as inde-
pendent bus masters.
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The DMA channels are initialized through their pro-
grammable registers. Once the transfer parame-
ters have been programmed, the DMA channel
must first be enabled and the transfer initialized.
Setting the EN bit in the respective DMA_CTRLx_0
register enables the DMA channel. Once enabled,
the DMA channel accepts requests. At that point,
the DMA accept requests but cannot service them.
A transfer is initialized by setting the INIT bit.
Upon initialization, the first DMA request loads the
start address and start count into their respective
counters. The INIT bit is reset by hardware and
the DMA controller services the request. Software
can detect that a transfer has been initiated when
the INIT bit is cleared. The next transfer parame-
ters can be updated and the INIT bit set.
Requests are processed on a cycle basis. Re-
quests lasting more than one clock cycle are inter-
preted as multiple requests. If the DMA cannot
process all the incoming requests, a Pending Re-
quest Counter keeps track of such requests. A
total of 64K pending requests are possible. If the
EN is cleared in the middle of a block transfer, any
subsequent requests are ignored by the DMA and
by the pending request counter. The counters can
be read through software until it is reset. The
counters are initialized either by the CLR bit or by
enabling the DMA channel.
In case a DMA channel is not responding properly,
it is possible to reset it through the CLR bit in the
control register. Once the CLR bit is set, the DMA
channel is in a reset state. It exits this state only
after the CLR bit is cleared. After a power-on reset
or other system-wide reset, CLR is set.
A block transfer normally completes when the
transfer counter reaches zero. At that point, de-
pending on the mode, the DMA transfer either
stops or continues. The DMA continues with the
next block transfer if the INIT bit is set, or if con-
tinuous mode is enabled. Resetting the DMA chan-
nel also terminates a block transfer. The latter
method should be used very carefully.
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Software can cleanly abort an operation in the mid-
dle of a DMA transfer. Once the user detects that
the current DMA transfer can be aborted, the DMA
channel can be disabled cleanly by clearing the EN
bit. The next step is to reset the DMA channel
logic, accomplished by setting the CLR bit. Only
one clock cycle is necessary to reset the DMA
channel logic. Once the CLR is cleared, the DMA
channel is again ready to use. Except for a few
important control bits (refer to the reset values of
each field of the DMA registers), the rest of the
configuration registers will have kept their previ-
ously programmed values. By writing a few com-
mand bits to the control register, the previous
transfer could be repeated.
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The DMA controller always does the read transfer
first and stores the data into its temporary FIFO.
Then it performs the write transfer.
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This section describes the basic DMA transfer
types and features. Some of these transfer modes