Specifications

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From the time an interrupt source is activated, the
longest response time is 12 machine cycles. This
includes
 1 machine cycle to detect the interrupt
 2 machine cycles to complete the IE, IP, EIE or
EIP access
 5 machine cycles to complete the MUL or DIV
instruction
 4 machine cycles to complete the hardware
LCALL to the interrupt vector location.
Thus in a single-interrupt system, the interrupt re-
sponse time is always more than 5 machine cycles
but not more than 12 machine cycles. The maxi-
mum latency of 12 machine cycles is 48 clock cy-
cles. In the original 8051, the maximum latency is
8 machine cycles or 96 clock cycles. Conse-
quently, the ZE5’s interrupt response time is two
times faster than an average 8051.
Table 38. Interrupt Response Latency
(Single-Interrupt System).
Minimum Maximum
Machine Cycles 5 12
Clock Cycles 20 48
Reset Conditions
Table 39. Reset Types and Affected Resources.
RESET CONDITION
Power-On Reset RST- Pin JTAG Command (FORCE_BRST) Application Reset (RSTC) Watchdog Timer Reset JTAG Command (J_RESET)
Device Resources Affected
8032 “Turbo” MCU
     
DMA Controller
  
Memory
Interface Unit (MIU)
  
Configuration
Registers (CRU)
  
Clock control
registers
 
JTAG Unit
 
Post-Reset Behavior
(Re-) Initialize
Device
  
Begin Executing
Code from 0000h
     
Several possible conditions reset the Zylogic ZE5
configurable system-on-chip. Different reset
sources affect the device differently.
For example, a Power-On Reset (POR) condition
resets all of the device functions including the 8032
“Turbo” microcontroller, peripherals connected to
the internal CSI bus, many of the internal system
registers (CRU), the clock logic, and the JTAG unit.
By contrast, asserting the RST- pin resets most of
the device, but leaves the clock control registers
and JTAG unit unaffected.
Finally, a watchdog reset or asserting the applica-
tion reset sideband signal, RSTC, only affects the
embedded 8032 microcontroller. All other system
logic is unaffected.
Table 39 summarizes the various reset conditions
and the system resources that each affects. The
table indicates how the device behaves after the
reset. Some reset conditions cause the device to
re-initialize and restart code execution from 0000h.
Others merely restart code execution.
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The on-chip analog circuitry continuously monitors
the VCC levels and detects a power on or power
fail condition. As long as VCC is below the thresh-
old VRST, the device remains in the reset condi-
tion. Once VCC goes above the VRST level, the
analog circuit releases the reset.
On-chip logic generates a power-on reset (POR)
when power is applied to the device, resetting all
device resources that can be reset. POR is re-
leased after a clock source is available (after the
first two rising clock edges).
The software should clear the POR flag after read-
ing it, otherwise it will not be possible to correctly
determine future reset sources. If the power fails,
i.e. falls below VRST, then the device again goes
into the reset state. When the power returns to the
proper operating levels, the device again performs
a power on reset and sets the POR flag.
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The RST- pin, when asserted Low, resets all inter-
nal resources except for the clock control registers
and the JTAG unit. The assertion of the reset is
asynchronous but its de-assertion is automatically
synchronized with bus clock signal, BCLK. A glitch
filter prevents glitches on the RST- pin lasting less
than 2ns. RST- should always be asserted with a
signal lasting more than 8 ns in duration.
The RST- pin can be disabled by two conditions.
First, the RST- pin is ignored if the CSoC is placed
in Secure mode by setting the MIU bit (SECU-
RITY.0) in the Security register. This condition is
cleared once power is removed from the device.
Second, a FORCE_NOBRST command can be
issued via the JTAG unit during debugging. This