Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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LCALL. The vector addresses for the different
sources are as shown in Table 37 Note that the
vector addresses are not evenly spaced in memory.
Execution continues from the vectored address
until an RETI instruction is executed. On execut-
ing the RETI instruction, the processor pops the
Stack and loads the PC with the contents at the
top of the stack. The user’s software must restore
the stack to its values prior to the hardware LCALL
when execution returns to the interrupted program.
All interrupt service routines end with the Return
From Interrupt (RETI) instruction. Note that a RET
instruction performs like a RETI instruction, but it
does not inform the Interrupt Controller when the
interrupt service routine is complete, leaving the
controller to think that the service routine is in pro-
gress.
Table 37. Vector locations for
interrupt sources.
Source
Vector
Address
Keil
Intr. #
High-Priority
Interrupt
0x0033 6
External Interrupt 0 0x0003 0
Timer 0 Overflow 0x000B 1
External Interrupt 1 0x0013 2
Timer 1 Overflow 0x001B 3
Serial Port 0x0023 4
Timer 2 Interrupt 0x002B 5
DMA 0x003B 7
Hardware
Breakpoint
0x0043 8
JTAG 0x004B 9
Software Breakpoint 0x0053 10
Watchdog Timer 0x0063 12
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There are three external interrupt sources in this
processor. The High-Priority Interrupt is supplied
via the HPINT sideband signal. This interrupt has
priority over all other interrupts and typically con-
nects to an external power-fail signal. The other
external interrupts are INTR0 and INTR1, also
available as sideband signals. These interrupts
can be programmed to be edge triggered or level
activated, by setting bits IT0 and IT1 in TCON SFR.
NOTE:
The polarity of the external interrupt sig-
nals, INTR0 and INTR1, are opposite that
of the original 8032. In the original
8032, these signals are falling-edge trig-
gered or active-Low level. In the ZE5
family, these signals are rising-edge trig-
gered or active-High level.
In the edge-triggered mode, the INTR0 and INTR1
sideband signals are sampled at C4 in every ma-
chine cycle. If the sample is Low in one cycle and
High in the next, then a low-to-high transition is
detected and the interrupts request flag IE0 or IE1
is set in the timer control register, TCON. The flag
bit then requests the interrupt. Because external
interrupts are sampled every machine cycle, they
must be held High or Low for at least one complete
machine cycle. The interrupt service routine auto-
matically clears the appropriate IE0 or IE1 flag.
In level activated mode, the requesting source
must hold the pin High until the interrupt is ser-
viced. The IE0 or IE1 flag is not cleared by the
hardware on entering the service routine.
If the interrupt continues to be held High—even
after the service routine is completed—then the
processor may acknowledge another interrupt re-
quest from the same source.
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The response time for each interrupt source de-
pends on several factors like nature of the interrupt,
the instruction currently executing, and wait-states
on the CSI bus.
External interrupts INTR0 and INTR1 are sampled
at C3 of every machine cycle and then their corre-
sponding interrupt flags IE0 and IE1 are set or re-
set. Similarly, the Serial port flags RI and TI are
set in C3. The Timer 0 and 1 overflow flags are
set at C3 of the machine cycle in which overflow
has occurred. These flag values are polled only in
the next machine cycle. If a request is active and
all three conditions are met, then the hardware-
generated LCALL is executed. This call itself
takes four machine cycles to complete.
Consequently, there is a minimum latency of five
machine cycles between the time the interrupt flag
is set and the interrupt service routine begins exe-
cuting. A longer response time should be antici-
pated if any of the following three conditions is met.
1. An interrupt of equal or higher priority is cur-
rently being serviced.
2. The current polling cycle is not the last ma-
chine cycle of the instruction currently being
executed.
3. The current instruction involves a write to IP,
IE, EIP or EIE registers and is not a RETI.
If a higher or equal priority interrupt is being ser-
viced, then the interrupt latency time depends on
the service routine currently executing. If the poll-
ing cycle is not the last machine cycle of the in-
struction being executed, then an additional delay
is introduced. The maximum response time—if no
other interrupt is currently being serviced—occurs
if the 8032 is performing a write to IE, IP, EIE or
EIP and then executes a MUL or DIV instruction.