Specifications

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rupt. However there is a predefined hierarchy

among the interrupts themselves. This hierarchy

helps the interrupt controller to resolve simultane-

ous requests having the same priority level.

The default hierarchy is defined as shown Table 35.

The interrupts are numbered starting from the

highest priority to the lowest. Some of the inter-

rupts have an individual priority bit that, when set,

places those interrupts in a higher-priority category.

The default priority remains for interrupts placed in

the higher-priority category.

Table 35. Priority structure of interrupts.

Source Flag

Priority

Level

Priority

Bit

High-Priority HPI

(highest)

External

Interrupt 0

IE0 2



Timer 0

Overflow

TF0 3



External

Interrupt 1

IE1 4



Timer 1

Overflow

TF1 5



Serial Port



Timer 2

Overflow

TF2

EXF2



DMA

OVR0

INIT0

TC0

OVR1

INIT1

TC1

Hardware

Breakpoint

BP0I

BP1I

JTAG JTAGI 10

Software Break-

point (A5 in-

struction)

EA5 11

Watchdog Timer WDIF

(lowest)



The interrupt flags are sampled in C2 of every ma-

chine cycle. In the same machine cycle, the sam-

pled interrupts are polled and their priority is re-

solved. If certain conditions are met, then the

hardware executes an internally generated LCALL

instruction that vectors the process to the appro-

priate interrupt vector address. The conditions for

generating the LCALL are

1. An interrupt of equal or higher priority is not

currently being serviced.

2. The current polling cycle is the last machine

cycle of the instruction currently being exe-

cuted.

3. The current instruction does not involve a write

to IP, IE, EIP or EIE registers and is not a

RETI.

An LCALL is only generated if all of the conditions

are met. The polling cycle is repeated every ma-

chine cycle, with the interrupts sampled in C2 of

the same machine cycle. If an interrupt flag is ac-

tive in one cycle but not responded to, and is not

active when the above conditions are met, the de-

nied interrupt will not be serviced. This means that

active interrupts are not remembered. Every poll-

ing cycle is new.

Table 36. Interrupt Sources and Reset Method.

Interrupt

Source Flag

Cleared by

Hardware

Cleared by

Software

HPINT HPI



INTR0 IE0

Edge-

triggered

Level-

triggered

Timer 0 TF0



INTR1 IE1

Edge-

triggered

Level-

triggered

Timer 1 TF1



Serial

Port



Timer 2

TF2

EXF2



OVR0



INIT0



TC0



OVR1



INIT1



DMA

Controller

TC1



Watchdog WDIF



The processor responds to a valid interrupt by exe-

cuting an LCALL instruction to the appropriate ser-

vice routine. Hardware may or may not clear the

flag that caused the interrupt, as shown in Table

36. For Timer interrupts, the TF0 or TF1 flags are

cleared by hardware whenever the processor vec-

tors to the appropriate timer service routine. With

External interrupts, INTR0 and INTR1, the flags

are cleared only if they are edge triggered. For

Serial interrupts, the flags are not cleared by hard-

ware. The ISR must poll to determine if the trans-

mitter or receiver generated the interrupt and clear

the appropriate flags. With the Timer 2 interrupt,

the flag is not cleared by hardware. The Power-

Fail Interrupt flag (PFI) and Watchdog timer inter-

rupt flag (WDIF) must be cleared by software. The

hardware LCALL behaves exactly like the software

LCALL instruction. This instruction saves the Pro-

gram Counter (PC) contents onto the Stack, but

does not save the Program Status Word (PSW).

The Program Counter (PC) is reloaded with the

vector address of the interrupt that caused the