Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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Absolute addressing is used to specify the destina-
tion address in ACALL and AJMP instructions.
The operand is an 11-bit address within the current
2K block of program memory.
In this mode of addressing, the 16-bit address is
generated by taking the five highest order bits of
the next instruction (PC + 2) and concatenating the
lowest order 11 bit field contained in the current
instruction. The resulting addressed location lies
within the 2K page of the Program Memory, rela-
tive to the first byte of the instruction following the
current instruction.
Example:
ACALL 0200h ; If the current instruction is at location
; 7FFFh, then a call will be made to the
; location 8200h
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Long addressing specifies the full 16-bit address
anywhere within the 64K program memory for the
LJMP and LCALL instructions.
Example:
LJMP 8000h ; Jump to location 8000h in program memory.
Interrupts
The Zylogic ZE5 has a three priority level interrupt
structure with 12 interrupt sources. Each of the
interrupt sources has an individual flag, interrupt
vector and enable bit. The standard 8032 micro-
controller interrupts have individual priority bits.
Furthermore, the interrupts—with the exception of
the High-Priority Interrupt—can be globally en-
abled or disabled.
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The external interrupt sideband signals, INTR0 and
INTR1, are either edge triggered or level triggered,
depending on bits IT0 and IT1 in the TCON regis-
ter. The flag bits IE0 and IE1 in the TCON register
generate the interrupt and indicate which interrupt
has occurred. When an external interrupt input
generates an interrupt, the appropriated flag bit is
cleared upon entering the Interrupt Service routine,
but only if the interrupt type is edge triggered. In
level activated mode, the external requesting
source controls the interrupt flag bit rather than the
on-chip hardware. For level-triggered interrupts,
the IE0 and IE1 flags are not cleared by hardware
and must be cleared by the software.
The TF0 and TF1 flags generate the Timer 0 and 1
Interrupts. These flags are set when Timer 0 and
Timer 1 overflow, respectively. Hardware auto-
matically clears the TF0 and TF1 flags when the
timer interrupt is serviced.
The Timer 2 interrupt is generated by a logical OR
of the TF2 and the EXF2 flags. These flags are
set by overflow/underflow or capture/reload events
in the Timer 2 operation. The hardware does not
clear these flags when a Timer 2 interrupt is exe-
cuted. Software has to resolve the cause of the
interrupt between TF2 and EXF2 and clear the ap-
propriate flag.
The Watchdog timer can be used as a system
monitor or a simple timer. In either case, the
Watchdog timer interrupt flag WDIF (WDCON.3) is
set when the time-out count is reached. If the in-
terrupt is enabled by the enable bit EIE.4, then an
interrupt occurs.
The serial port also generates interrupts on data
reception or transmission. However, there is only
one interrupt source from the Serial block, the logic
OR of the RI and TI bits in the SCON SFR. These
bits are not automatically cleared by the hardware
and the software must clear these bits.
The High-Priority Interrupt flag, HPI, (WDCON.4) is
set when the HPINT sideband signal is asserted.
If this interrupt is enabled then an interrupt occurs.
The high-priority interrupt has the highest priority
over all the interrupts. The user cannot alter its
priority but it can be enabled or disabled via soft-
ware. The EHPI bit enables the high-priority inter-
rupt. This bit is not controlled by the global inter-
rupt enable EA.
The standard 8032 interrupt flags that generate
interrupts can be set or reset by writing to the ap-
propriate registers. Consequently, software can
generate interrupts. The addition ZE5 interrupts
(DMA, JTAG, software and hardware breakpoint)
can only by reset by software. Individual interrupts
can be enabled or disabled by setting or clearing a
bit in the IE or the EIE SFR. IE also has a global
enable/disable bit, EA, which is cleared to disable
all the interrupts at once, except for the high-
priority interrupt (HPI), which is unaffected by EA.
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There are three priority levels for the interrupts,
highest, high and low. The high-priority interrupt
HPI has the highest priority. No other interrupt can
have this priority. Naturally, a higher priority inter-
rupt cannot be interrupted by a lower priority inter-
rupt. However there is a predefined hierarchy
among the interrupts themselves. This hierarchy
helps the interrupt controller to resolve simultane-
ous requests having the same priority level.
There are three priority levels for the interrupts,
highest, high and low. The high-priority interrupt
HPI has the highest priority. No other interrupt can
have this priority. Naturally, a higher priority inter-
rupt cannot be interrupted by a lower priority inter-