Specifications
Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 64
E
E
x
x
t
t
e
e
n
n
d
d
e
e
d
d
I
I
n
n
t
t
e
e
r
r
r
r
u
u
p
p
t
t
E
E
n
n
a
a
b
b
l
l
e
e
- --EWDI----
76543210
Mnemonic: EIE Address: E8h
EIE.7-5 are reserved bits and return a High when
read.
EWDI enables the Watchdog timer interrupt.
EIE.3-0 are reserved bits and return a High when
read.
The EIE SFR is set to 11101111b on any reset.
This SFR has unrestricted read/write access.
B
B
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
Mnemonic: B Address: F0h
The B register is used during multiply and divide
operations. For other instructions, it can be treated
as another scratch pad register.
The B register is reset to 00h on any reset
This SFR has unrestricted read/write access.
E
E
x
x
t
t
e
e
n
n
d
d
e
e
d
d
I
I
n
n
t
t
e
e
r
r
r
r
u
u
p
p
t
t
P
P
r
r
i
i
o
o
r
r
i
i
t
t
y
y
- --PWDI----
76543210
Mnemonic: EIP Address: F8h
EIP.7-5 are reserved bits and return a High when
read.
PWDI, when set, defines the Watchdog timer as a
higher-priority interrupt.
EIP.3-0 are reserved bits and return a High when
read.
The EIP SFR is set to 11101111b on any reset.
This SFR has unrestricted read/write access.
Instruction Set
The Zylogic configurable system-on-chip executes
all the instructions of the standard 8032 family.
The operation of these instructions, their effect on
the flag bits and the status bits is exactly the same.
However, timing of these instructions is different.
There are two reasons for the timing differences.
First, each 8032 “Turbo” microcontroller machine
cycle takes 4 clock periods, while in the original
8032 requires 12 clock periods. Second, the
“Turbo” microcontroller only performs one fetch per
machine cycle, i.e. 4 clocks per fetch. The stan-
dard 8032 can require two fetches per machine
cycle, or 6 clocks per fetch.
The 8032 "Turbo" microcontroller's advantage is
that there is only one fetch per machine cycle. In
most cases, the number of machine cycles is equal
to the number of operands required by the instruc-
tion. Jumps and calls require an additional cycle to
calculate the new address. Overall, the 8032
"Turbo" microcontroller reduces the number of
dummy fetches and wasted cycles, thereby im-
proving efficiency compared to the original 8032.
A
A
d
d
d
d
r
r
e
e
s
s
s
s
i
i
n
n
g
g
M
M
o
o
d
d
e
e
s
s
The 8032 microcontroller uses eight different ad-
dressing modes. These modes are as follows, with
detailed descriptions below.
1. Register addressing
2. Direct addressing
3. Register Indirect addressing
4. Immediate addressing
5. Base register plus Index register Indirect ad-
dressing
6. Relative addressing
7. Absolute addressing
8. Long addressing
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
A
A
d
d
d
d
r
r
e
e
s
s
s
s
i
i
n
n
g
g
Register addressing uses the eight working regis-
ters (R0-R7) of the current register bank located in
the scratchpad RAM. The last three bits in the in-
struction op-code indicate the selected register.
The current register bank is one of four register
banks residing in the scratchpad RAM. The two
bits RS1-RS0 in the Program Status Word (PSW)
select the working bank. Consequently, the same
instruction can access different registers simply by
switching between banks. ACC, B, the current
DPTR determined by DPS.0, and CY can also be
addressed as registers.
Example:
ADDC A, R2 ; Add Accumulator to register R2 with carry.
DEC R7 ; Decrement contents of register R7
CLR A ; Clear the Accumulator
SETB C ; Set the Carry flag (Boolean Processor
; Accumulator)
D
D
i
i
r
r
e
e
c
c
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
i
i
n
n
g
g
Direct addressing is the only method to refer to the
Special Function Registers (SFRs). This mode
accesses the entire lower 128 bytes of the
Scratchpad RAM.
Direct addressing also applies to bit operations.
The Scratchpad RAM area from 20h to 2Fh is bit-
addressable. The bits in this area have their own
unique bit addresses from 00h to 7Fh. These bits
may be addressed by directly specifying the bit
address. Several SFRs are also bit addressable.