Specifications

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F0 is User flag 0, a general-purpose flag that can
be set or cleared by the user by software.
RS.1-0 select the active Register bank as shown in
Table 34.
Table 34. Register Bank Select.
RS1 RS0
Register
bank Address
0 0 0 00-07h
0 1 1 08-0Fh
1 0 2 10-17h
1 1 3 18-1Fh
OV is the Overflow flag. Set by arithmetic opera-
tions. Indicates that two most significant accumu-
lator bits are different. Used primarily with signed
or twos-compliment data to indicate that the arith-
metic operation overflowed the accuracy of the
accumulator.
F1 is User Flag 1, a general-purpose flag that can
be set or cleared by the user by software
P is the Parity flag. This bit is set or cleared by
hardware to indicate odd/even number of 1’s in the
accumulator.
The PSW SFR is set to 00h by a reset.
There is unrestricted read/write access to this SFR.
W
W
a
a
t
t
c
c
h
h
d
d
o
o
g
g
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- POR EHPI HPI WDIF WTRF EWT RWT
76543210
Write protected by Timed-Access (TA) register
Mnemonic: WDCON Address: D8h
WDCON.7 is un-implemented and returns a High
when read.
POR is the Power-On Reset flag. Hardware sets
this flag on a power-up condition. This flag can be
read or written by software. A write by software is
the only way to clear this bit once it is set.
EHPI is the Enable High-Priority Interrupt bit.
When set to 1, this bit enables the High-Priority
Interrupt. If cleared, then the high-priority side-
band signal (HPINT) is ignored.
HPI is the High-Priority Interrupt flag. This flag is
set by hardware whenever the high-priority side-
band signal (HPINT) is asserted. Software must
clear this bit. Writing a 1 to this bit forces an inter-
rupt if the EHPI bit is also set.
NOTE:
Some of the bits in the Watchdog Control
register (WDCON) are protected. They
cannot be accidentally overwritten by an
errant program. Before attempting to
change the RWT, EWT, WDIF, or POR
bits, you must write the proper sequence
to the Timed Access (TA) register.
WDIF is the Watchdog Timer Interrupt Flag. If the
watchdog interrupt is enabled, hardware sets this
bit to indicate that a watchdog interrupt occurred.
If the interrupt is not enabled, then this bit indicates
that the time-out period has elapsed.
WTRF is the Watchdog Timer Reset Flag. Hard-
ware sets this bit whenever the watchdog timer
causes a reset. Software must clear this bit. A
Power-On or System Reset event also clears the
bit. This bit helps software to determine the cause
of a reset. If EWT = 0, the watchdog timer has no
affect on this bit.
EWT is the Enable Watchdog Timer reset. Setting
this bit enables the Watchdog Timer Reset function.
RWT is the Reset Watchdog Timer bit. This bit
forces the watchdog timer into a known state. Set-
ting this bit via software resets the watchdog timer,
usually before a watchdog time-out occurs. If the
RWT bit is not set before a watchdog time-out
happens, then two possible subsequent events
occur. If a watchdog time-out occurs while the
EWDI (EIE.4) interrupt enable bit is set, then a
watchdog interrupt results. If a watchdog time-out
occurs, then 512 clock cycles later, the Watchdog
Timer resets the MCU if EWT is set. Setting RWT
during this 512 clock period resets the Watchdog
Timer, avoiding the MCU reset. This bit is self-
clearing.
The WDCON SFR is set to a 1x0x0xx0b on an ex-
ternal reset, an 'x' indicating a bit unaffected by
reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF
is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-
on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read ac-
cess. POR, EWT, WDIF and RWT require timed
access write. The remaining bits have unrestricted
write accesses.
A
A
c
c
c
c
u
u
m
m
u
u
l
l
a
a
t
t
o
o
r
r
Mnemonic: ACC Address: E0h
ACC.7-0, the A or ACC register, is the standard
8032 accumulator
The ACC is reset to 00h on any reset
This SFR has unrestricted read/write access.