Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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Timer 2 by clearing this bit preserves the current
count value in TH2, TL2.
C/T2 is the Counter/Timer select bit. This bit de-
termines whether Timer 2 functions as a timer
(counting clock cycles) or as a counter. Independ-
ent of this bit, the timer runs at 2 clocks per tick
when used in baud rate generator mode. If it is set
to 0, then Timer 2 operates as a timer at a speed
depending on T2M bit (CKCON.5). Otherwise, it
counts falling edges on the T2 sideband signal.
CP/RL2 is the Capture/Reload Select bit. This bit
determines whether the capture or reload function
is used for Timer 2. If either RCLK or TCLK is set,
this bit will not function and the timer will function in
an auto-reload mode following each overflow. If
the bit is 0, then auto-reload occurs whenever
Timer 2 overflows or a falling edge is detected on
T2EX if EXEN2 = 1. If this bit is 1, Then Timer 2
captures happen whenever a falling edge is de-
tected on T2EX if EXEN2 = 1.
The T2CON is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
T
T
i
i
m
m
e
e
r
r
2
2
M
M
o
o
d
d
e
e
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- - - - - - - DCEN
76543210
Mnemonic: T2MOD Address: C9h
DCEN is the Down Count Enable bit. This bit, in
conjunction with the T2EX sideband signal controls
the direction that Timer 2 counts in 16-bit auto-
reload mode.
When DCEN is set, Timer 2 counts up or down,
controlled by the T2EX sideband signal. When
High, T2EX causes Timer 2 to increment. When
Low, Timer 2 decrements. When DCEN=0, Timer
2 only counts up.
The T2MOD is reset to FEh by a reset.
There is unrestricted read/write access to this SFR.
T
T
i
i
m
m
e
e
r
r
2
2
C
C
a
a
p
p
t
t
u
u
r
r
e
e
L
L
S
S
B
B
Mnemonic: RCAP2L Address: CAh
RCAP2L is the least-significant byte of the Timer 2
capture register. This register is used to capture
the TL2 value when a Timer 2 is configured in cap-
ture mode. RCAP2L is also used as the least-
significant byte of a 16-bit reload value when Timer
2 is configured in auto-reload mode.
The RCAP2L SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
Registers RCAP2H and RCAP2L potentially also
control the baud for the 8032's serial port, when
the serial port operates in variable baud rate mode,
i.e., Mode 1 or Mode 3.
The equation for controlling the baud rate is shown
below, where {RCAP2H,RCAP2L} represent a 16-
bit binary value, F is the bus clock frequency, and
Baud is the desired rate.
⎟
⎠
⎞
⎜
⎝
⎛
•
−=
Baud32
F
65536ROUNDRCAP2L}{RCAP2H,
busclock
The resulting value may be a non-integer. Round
the value up or down, whichever most closely
matches the desired baud rate. In some instances,
selecting a different bus clock frequency will result
in a value closer to the desired baud rate.
T
T
i
i
m
m
e
e
r
r
2
2
C
C
a
a
p
p
t
t
u
u
r
r
e
e
M
M
S
S
B
B
Mnemonic: RCAP2H Address: CBh
RCAP2H is the least-significant byte of the Timer 2
capture register. This register is used to capture
the TH2 value when a Timer 2 is configured in cap-
ture mode. RCAP2H is also used as the most-
significant byte of a 16-bit reload value when Timer
2 is configured in auto-reload mode.
The RCAP2H SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
Registers RCAP2H and RCAP2L potentially also
control the baud for the 8032's serial port, when
the serial port operates in variable baud rate mode,
i.e., Mode 1 or Mode 3. See description for Timer
2 Capture LSB.
T
T
i
i
m
m
e
e
r
r
2
2
L
L
S
S
B
B
Mnemonic: TL2 Address: CCh
TL2 is the least-significant byte of Timer 2.
The TL2 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
T
T
i
i
m
m
e
e
r
r
2
2
M
M
S
S
B
B
Mnemonic: TH2 Address: CDh
TH2 is the most-significant byte of Timer 2.
The TH2 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
P
P
r
r
o
o
g
g
r
r
a
a
m
m
S
S
t
t
a
a
t
t
u
u
s
s
W
W
o
o
r
r
d
d
CY AC F0 RS1 RS0 OV F1 P
76543210
Mnemonic: PSW Address: D0h
CY is the Carry flag. This bit is set by arithmetic
operations that generate a carry in the ALU. It is
also used as the accumulator for the bit operations.
AC is the Auxiliary carry bit. This bit is Set when
the previous operation resulted in a carry during an
addition operation or resulted in a borrow during a
subtraction from the high order nibble.