Specifications

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SADDR is used only during multiple MCU opera-
tions involving the serial port.
SADDR is loaded with the given or broadcast ad-
dress for the serial port if the ZE5 is used as a
slave processor during multiprocessor communica-
tions.
The SADDR SFR is set to 00h by a reset.
There is unrestricted read/write access to this SFR.
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- - PT2 PS PT1 PX1 PT0 PX0
76543210
Mnemonic: IP Address: B8h
The IP.7-6 bits are un-implemented and return a
High when read.
PT2, when set, defines the Timer 2 interrupt as a
higher priority interrupt.
PS, when set, defines the Serial port interrupt as a
higher priority interrupt.
PT1, when set, defines the Timer 1 interrupt as a
higher-priority interrupt.
PX1, when set, defines the External Interrupt 1 as
a higher-priority interrupt.
PT0, when set, defines the Timer 0 interrupt as a
higher-priority interrupt.
PX0, when set, defines External Interrupt 0 as a
higher-priority interrupt.
The IP SFR is set to 11000000b by a reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: SADEN Address: B9h
The SADEN register enables the Automatic Ad-
dress Recognition feature of the Serial port. When
a bit in the SADEN is set to 1, the same bit location
in SADDR is compared with the incoming serial
port data. When SADEN is 0, then the bit becomes
a don’t-care in the comparison. When all the bits
of SADEN are 0, an interrupt occurs for any incom-
ing address.
The SADEN SFR is set to 00h by a reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: TA Address: C7h
The Timed Access (TA) register controls the ac-
cess to protected Watchdog controller bits in the
8032 microcontroller. A separate timed access
register (PROTECT) supports the secure initializa-
tion mode. To access protected bits, application
software must first write AAh to the TA SFR. This
must be immediately followed by a write of 55h to
TA. This opens a window for three machine cycles,
during which time software can write to these pro-
tected bits.
The TA returns FFh when read.
There is unrestricted write access to this SFR, a
read is not required.
Example:
MOV TA, 0AAH ; Write ‘AA’ followed by ‘55’ to open
; window
MOV TA, 055H ; Window now open for three machine
; cycles
SETB RWT ; Reset watchdog timer
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TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
76543210
Mnemonic: T2CON Address: C8h
TF2 is the Timer 2 overflow flag. This bit is set
when Timer 2 overflows. It is also set when the
count equals the capture register value while in
down count mode. It can be set only if RCLK and
TCLK are both 0. It is only cleared by software.
Software can also set or clear this bit.
EXF2 is the Timer 2 External Flag. A falling-edge
transition on the T2EX sideband signal or a Timer
2 underflow/overflow condition sets this flag based
on the CP/RL2, EXEN2 and DCEN bits. If set by a
falling-edge transition, this flag must be cleared by
software. Setting this bit in software or a detected
falling-edge transition on T2EX pin forces a timer
interrupt, if enabled.
RCLK is the Receive clock flag. This bit deter-
mines the serial port timebase when receiving data
in serial modes 1 or 3. If this bit is 0, then Timer 1
overflow is used for baud rate generation, else
Timer 2 overflow is used. Setting this bit forces
Timer 2 into baud-rate generator mode.
TCLK is the Transmit clock flag. This bit deter-
mines the serial port timebase when transmitting
data in serial modes 1 and 3. If it is set to 0, the
Timer 1 overflow is used to generate the baud rate
clock, else Timer 2 overflow is used. Setting this
bit forces Timer 2 into baud-rate generator mode.
EXEN2 is the Timer 2 External Enable bit. This bit
enables the capture/reload function on the T2EX
sideband signal if Timer 2 is not generating baud
clocks for the serial port. If this bit is 0, then the
T2EX sideband signal is ignored, else a falling-
edge transition detected on the T2EX sideband
signal results in capture or reload.
TR2 is the Timer 2 Run Control bit. This bit en-
ables/disables the operation of Timer 2. Halting