Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 60
T1M is the Timer 1 clock select bit. When T1M is
set to 1, Timer 1 uses a divide-by-4 clock. When
set to 0, Timer 1 uses an 8032-compatible divide-
by-12 clock.
T0M is the Timer 0 clock select bit. When T0M is
set to 1, Timer 0 uses a divide-by-4 clock. When
set to 0, Timer 0 uses an 8032-compatible divide-
by-12 clock.
CKCON.2-0 are reserved.
The CKCON SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
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SM0/FE SM1 SM2 REN TB8 RB8 TI RI
76543210
Mnemonic: SCON Address: 98h
SM0/FE performs as either Serial port, Mode 0 bit
or as the Framing Error Flag. The SMOD0 bit in
PCON SFR determines whether this bit acts as
SM0 or as FE. The operation of SM0 is described
in Table 33.
When used as FE, this bit is set to indicate an in-
valid stop bit. Software must clear the FE condition.
SM1 is the Serial port Mode bit 1.
SM2 is the Serial port Mode bit 2, which controls
multiple MCU communication. Setting this bit en-
ables the multiprocessor communication feature in
Mode 2 and 3. In Mode 2 or 3, if SM2 is set, then
RI is not activated if the received 9th data bit (RB8)
is 0. In Mode 1, if SM2 = 1, then RI is only acti-
vated if a valid stop bit is received. In Mode 0, the
SM2 bit controls the serial port clock. If cleared,
then the serial port runs at 1/12 the system clock
frequency, providing compatibility with the stan-
dard 8032. When set, the serial clock is 1/4 the
system clock frequency, resulting in faster syn-
chronous serial communication.
Table 33. Serial Mode Control Values.
SM0 SM1 Mode
Descrip-
tion Length Baud rate
0 0 0 Synch. 8
BUSCLK
÷4/÷12
0 1 1 Asynch. 10 variable
1 0 2 Asynch. 11
BUSCLK
÷64/÷32
1 1 3 Asynch. 11 variable
REN is the Receiver enable bit. Setting this bit to
1 enables serial reception, else reception is dis-
abled.
TB8 is the 9th bit to be transmitted in Modes 2 and
3. This bit is set and cleared by software as de-
sired.
RB8 is the received 9th data bit in Modes 2 and 3.
In mode 1, if SM2 = 0, RB8 is the received stop bit
value. In Mode 0, it has no function.
TI is the Transmit interrupt flag. This flag is set by
hardware at the end of the 8th bit time in mode 0,
or at the beginning of the stop bit in all other
modes during serial transmission. This bit must be
cleared by software.
RI is the Receive interrupt flag. This flag is set by
hardware at the end of the 8th bit time in mode 0,
or halfway through the stop bits time in the other
modes during serial reception. However, the re-
striction on SM2 applies on this bit. This bit can be
cleared only by software
The SCON SFR is set to 00h by a reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: SBUF Address: 99h
SBUF.7-0 is the serial data, read from or written to
this location. It actually consists of two separate 8-
bit registers. One is the receive register and the
other is the transmit buffer.
Any read access gathers data from the receive
data buffer, while write transfers are to the transmit
data buffer.
The SBUF SFR is set to 00h by a reset.
There is unrestricted read/write access to this SFR.
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EA - ET2 ES ET1 EX1 ET0 EX0
76543210
Mnemonic: IE Address: A8h
EA, when set, is the global enable bit and enables
all interrupts. When cleared, this bit disables all
interrupts, except for HPINT.
IE.6 is an un-implemented bit. It returns a High
when read.
ET2, when set, enables the Timer 2 interrupt.
ES, when set, enables the Serial interrupt.
ET1, when set, enables the Timer 1 interrupt.
EX1, when set, enables External interrupt 1.
ET0, when set, enables the Timer 0 interrupt.
EX0, when set, enables External interrupt 0.
The IE SFR is set to 01000000b by a reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: SADDR Address: A9h