Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 6
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The ZE5's 8032-based microcontroller has three
16-bit timers that are functionally similar to the tim-
ers of the original 8032 family. When used as tim-
ers, they optionally operate at either 4 clocks or 12
clocks per count, thus providing a mode that emu-
lates the timing of the original 8032.
The ZE5 also features a protected watchdog timer.
This timer is used as a system monitor or to time a
very long period.
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The Interrupt structure in the Zylogic configurable
system-on-chip is slightly different from that of the
original 8032. Due to the presence of additional
features and peripherals, the number of interrupt
sources and vectors is increased.
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The original 8032 had only one 16-bit Data Pointer
(DPL, DPH). In the ZE5, there is an additional 16-
bit Data Pointer (DPL1, DPH1). This new Data
Pointer inhabits two previously unused SFR loca-
tions in the original 8032.
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Like the original 80C31, the ZE5 provides Idle and
Power-Down modes of operation. Idle mode stops
the MCU while the timers, serial port and interrupt
block continues to operate. Power-Down mode
optionally stops all the clocks and completely halts
chip operation, the lowest power-consumption
state.
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The Zylogic configurable system-on-chip has an
on-chip Power-On Reset facility. This eliminates
the external capacitor-resistor network required in
original 8032 designs.
DMA Controller
The Zylogic ZE5's direct memory access (DMA)
controller contains two independent channels.
Each channel is autonomous from the 8032 micro-
controller, freeing the processor from mundane,
performance-stealing, data transfer operations.
Each channel is designed to transfer a byte of data
on each clock cycle, maximizing the data transfer
bandwidth. Several different data transfer modes
are available including those between memory and
a device, in any direction. A device associates
Control Logic
DMA Channel 0 DMA Channel 1
FIFO
FIFO
FIFO
FIFO
CRC
Address Bus and Data Write Bus
Data Read Bus
Pending
Requests
Counter
Transfer
Counter
Address
Counter
Bus Request/Grant Bus Request/Grant
Figure 4. Block diagram of the embedded two-channel DMA controller.