Specifications
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the interrupt was edge triggered. Otherwise, it
tracks the value that appears the INIT0 sideband
signal.
IT0 is the Interrupt 0 type control bit. It is set by
software to specify a rising-edge trigger, cleared to
specify an active-High level-triggered external in-
put.
The TCON SFR is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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GATE C/T M1 M0 GATE C/T M1 M0
76543210
Timer 1 Timer 0
Mnemonic: TMOD Address: 89h
GATE is the Gating control bit. When this bit is set,
Timer/counter x is enabled only while INTRx pin is
high and TRx control bit is set. When GATE is
cleared, the TRx bit (TR0 for Timer 0, TR1 for
Timer 1) enables the timer when set.
C/T is the Timer or Counter Select bit. When
cleared, the timer increments on internal clocks.
When set, the timer counts high-to-low edges of
the Tx (T0 for Timer 0, T1 for Timer 1) sideband
signal.
Table 31. Timer 0 and Timer 1
Mode Select Bits.
M1 M0 Mode
0 0 Mode 0: 8-bits with 5-bit pre-scaler.
0 1 Mode 1: 16-bits, no pre-scaler.
1 0
Mode 2: 8-bits with auto-reload from
THx
1 1
Mode 3: (Timer 0) TL0 is an 8-bit
timer/counter controlled by the Timer 0
control bits. TH0 is a 8-bit timer only
controlled by Timer 1 control bits.
(Timer 1) Timer/counter is stopped.
M1 and M0 are the Mode Select bits. They control
the operation of the Timer/Counter as defined in
Table 31.
The TMOD is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: TL0 Address: 8Ah
TL0.7-0 is the least-significant byte of Timer 0.
The TL0 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: TL1 Address: 8Bh
TL1.7-0 is the least-significant byte of Timer 1.
The TL1 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: TH0 Address: 8Ch
TH0.7-0 is the most-significant byte of Timer 0.
The TH0 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
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Mnemonic: TH1 Address: 8Dh
TH1.7-0 is the most-significant byte of Timer 1.
The TH1 SFR is set to 00h on any reset.
There is unrestricted read/write access to this SFR.
TH1 potentially also controls the baud for the 8032'
serial port, when the serial port operates in vari-
able baud rate mode, i.e., Mode 1 or Mode 3.
The equation for controlling the baud rate is shown
below, where SMOD is PCON.7, F is the bus clock
frequency, and Baud is the desired rate.
⎟
⎟
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−=
Baud384
F2
256ROUND{TH1}
busclock
SMOD
The resulting value may be a non-integer. Round
the value up or down, whichever most closely
matches the desired baud rate. In some instances,
selecting a different bus clock frequency will result
in a value closer to the desired baud rate.
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WD1 WD0 T2M T1M T0M - - -
76543210
Mnemonic: CKCON Address: 8Eh
WD1-0 are the Watchdog timer mode select bits.
These bits determine the time-out period for the
watchdog timer. For all four of the time-out options,
the reset time-out is 512 clocks after the interrupt
time-out period, as shown in Table 32.
Table 32. Watchdog Timer Modes.
WD1 WD0
Interrupt
time-out
Reset
time-out
0 0 2
17
2
17
+ 512
0 1 2
20
2
20
+ 512
1 0 2
23
2
23
+ 512
1 1 2
26
2
26
+ 512
T2M is the Timer 2 clock select bit. When T2M is
set to 1, Timer 2 uses a divide-by-4 clock. When
set to 0, Timer 2 uses an 8032-compatible divide-
by-12 clock.