Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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instructions using DPTR will then access DPL1
and DPH1 in place of DPL and DPH. If
DPL1/DPH1 are not used, then they can be used
an conventional register locations.
The DPL1 SFR is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
76543210
Mnemonic: DPH1 Address: 85h
This is the high byte of the additional 16-bit data
pointer added to the Zylogic configurable system-
on-chip. The user can switch between DPL/DPH
and DPL1/DPH1 simply by setting DPS = 1. The
instructions using DPTR will then access DPL1
and DPH1 in place of DPL and DPH. If
DPL1/DPH1 are not used as a data pointer, then
they can be used as conventional register loca-
tions.
The DPH1 SFR is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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RESERVED (Reads = 0)
DPS.0
76543210
Mnemonic: DPS Address: 86h
DPS.0 selects either the DPL/DPH pair or the
DPL1/DPH1 pair as the active Data Pointer. When
set to 1, DPL1/DPH1 is selected, else DPL/DPH is
selected.
DPS.1-7 are reserved but will read 0.
The DPS SFR is reset to 00h by a reset and se-
lects the standard DPTR by default.
There is unrestricted read/write access to this SFR.
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SMOD SMOD0 - - GF1 GF0 PD IDL
76543210
Mnemonic: PCON Address: 87h
SMOD, when set, doubles the serial baud rate
when the serial port is in Modes 1, 2, and 3.
SMOD0 is the Framing Error Detection Enable.
When SMOD0 is set to 1, then SCON.7 indicates a
Frame Error and acts as the FE flag. When
SMOD0 is 0, then SCON.7 behaves as a standard
8032 function.
GF1-0 are two general-purpose user flag bits.
Setting the PD bit causes the configurable system-
on-chip to go into the power-down mode. In this
mode, all the clocks are stopped and program exe-
cution is halted. While in power-down mode, addi-
tional low-power options are enabled, controlled by
the PWDSEL. See "Clocking and Global Signal
Distribution" for more details.
Setting the IDL bit causes the 8032 "Turbo" micro-
controller to go into the IDLE mode. In this mode,
the clock to the microcontroller is stopped, halting
program execution. However, the clock to the se-
rial, timer and interrupt blocks is not stopped, and
these blocks continue operating unhindered.
The PCON SFR is reset to 00110000b by a reset.
There is unrestricted read/write access to this SFR.
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TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
76543210
Mnemonic: TCON Address: 88h
TF1 is the Timer 1 overflow flag. This bit is set
when Timer 1 overflows and is cleared automati-
cally when the program executes a Timer 1 inter-
rupt service routine. Software can also set or clear
this bit.
TR1 is the Timer 1 run control bit. This bit is set or
cleared by software to turn Timer 1 on or off.
TF0 is the Timer 0 overflow flag. This bit is set
when Timer 0 overflows and is cleared automati-
cally when the program executes a timer 0 inter-
rupt service routine. Software can also set or clear
this bit.
TR0 is the Timer 0 run control bit. This bit is set or
cleared by software to turn Timer 0 on or off.
IE1 is the Interrupt 1 edge-detect flag. It is set by
hardware when an edge/level is detected on the
INTR1 sideband signal. This bit is cleared by hard-
ware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise, it
tracks the value that appears on the INIT1 side-
band signal.
NOTE:
The polarity of the external interrupt sig-
nals, INTR0 and INTR1, are opposite that
of the original 8032. In the original
8032, these signals are falling-edge trig-
gered or active-Low level. In the ZE5
family, these signals are rising-edge trig-
gered or active-High level.
IT1 is the Interrupt 1 type control bit. It is set by
software to specify a rising-edge trigger, cleared to
specify an active-High level-triggered external in-
put.
IE0 is the Interrupt 0 edge-detect flag. It is set by
hardware when an edge/level is detected on the
INTR0 sideband signal. This bit is cleared by hard-
ware when the service routine is vectored to only if