Specifications

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The 8032 uses Special Function Registers (SFRs)
to control and monitor peripherals and their modes.
The SFRs reside in the locations 80-FFh and are
accessed by direct addressing only. Some of the
SFRs are bit addressable. This allows a program
to modify a particular bit without changing the oth-
ers. The bit-addressable SFRs are those with ad-
dresses that end in 0 or 8. The 8032 "Turbo" mi-
crocontroller contains all the SFRs present in the
original 8032. However some previously unused
SFRs locations are added. The list of the SFRs is
shown in Table 30 with eight locations per row.
Empty locations indicate that these are no SFR
registers at these locations. When a bit or register
is not implemented, it returns a High when read.
A brief description of the SFRs now follows.
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SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
76543210
Mnemonic: SP Address: 81h
The Stack Pointer points to the current top of the
stack, located in the scratchpad RAM.
The SP SFR is set to 07h on any reset.
There is unrestricted read/write access to this SFR.
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DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0
76543210
Mnemonic: DPL Address: 82h
This is the low byte of the standard 8032 16-bit
data pointer. The DPL is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0
76543210
Mnemonic: DPH Address: 83h
This is the high byte of the standard 8032 16-bit
data pointer.
The DPH SFR is reset to 00h by a reset.
There is unrestricted read/write access to this SFR.
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DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
76543210
Mnemonic: DPL1 Address: 84h
This is the low byte of the additional 16-bit data
pointer added to the Zylogic configurable system-
on-chip. The user can switch between DPL/DPH
and DPL1/DPH1 simply by setting the DPS bit
(DPS.0) in the Data Pointer Select register. The
Table 30. Special Function Register (SFR) Locations.
F8h
EIP
F0h
B
E8h
EIE
E0h
ACC
D8h
WDCON
D0h
PSW
C8h
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
C0h
TA
B8h
IP SADEN
B0h
P3*
A8h
IE SADDR
A0h
P2*
98h
SCON SBUF
90h
P1*
88h
TCON TMOD TL0 TL1 TH0 TH1 CKCON
80h
P0* SP DPL DPH DPL1 DPH1 DPS PCON
indicates a bit-addressable location.
indicates an unused SFR register location, available for use by a “soft” module
Px* — the PIO ports P0 through P3 are implemented in CSL logic. Their SFR locations are exported. There are
special precautions when exporting the P2 port (see Register Indirect Addressing section).