Specifications
Zylogic ZE5 Configurable System-on-Chip Platform
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W
W
o
o
r
r
k
k
i
i
n
n
g
g
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
s
s
There are four sets of working registers, each con-
sisting of eight 8-bit registers. These are named
Banks 0, 1, 2, and 3. Individual registers within
these banks are directly accessed by separate
instructions. These individual registers are named
as R0, R1, R2, R3, R4, R5, R6 and R7. However,
the 8032 operates with only one particular bank at
a time. One of the four banks is selected by set-
ting the RS1-RS0 bits in the PSW. The R0 and R1
registers store the address for indirect accessing.
B
B
i
i
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
a
a
b
b
l
l
e
e
L
L
o
o
c
c
a
a
t
t
i
i
o
o
n
n
s
s
The scratchpad RAM area from location 20h to
2Fh is both byte- and bit-addressable. A bit within
this region is individually addressed using the ap-
propriate instruction. In addition, some of the
SFRs are also bit addressable. The instruction
decoder is able to distinguish a bit access from a
byte access by the type of the instruction itself. An
SFR whose address ends in a 0 or 8 is bit ad-
dressable.
S
S
t
t
a
a
c
c
k
k
The scratchpad RAM can be used for the stack.
This area is selected using the Stack Pointer (SP),
which stores the address of the top of the stack.
Whenever a jump, call, or interrupt is invoked, the
return address is placed on the stack. There is no
restriction as to where the stack can begin in the
RAM. By default however, the Stack Pointer con-
tains 07h at reset, though the user can change this
to any desired value. The SP points to the last
used location. Therefore, the SP is incremented
and then address pushed onto the stack. Con-
versely, while popping from the stack, the contents
are first read, and then the SP is decremented.
FFh
80h
Scratchpad RAM (Indirect Only)
SFR (Direct Only)
7Fh
30h
Direct RAM
2Fh
7F 7E 7D 7C 7B 7A 79 78
2Eh
77 76 75 74 73 72 71 70
2Dh
6F 6E 6D 6C 6B 6A 69 68
2Ch
67 66 65 64 63 62 61 60
2Bh
5F 5E 5D 5C 5B 5A 59 58
2Ah
57 56 55 54 53 52 51 50
29h
4F 4E 4D 4C 4B 4A 49 48
28h
47 46 45 44 43 42 41 40
27h
3F 3E 3D 3C 3B 3A 39 38
26h
37 36 35 34 33 32 31 30
25h
2F 2E 2D 2C 2B 2A 29 28
24h
27 26 25 24 23 22 21 20
23h
1F 1E 1D 1C 1B 1A 19 18
22h
17 16 15 14 13 12 11 10
21h
0F 0E 0D 0C 0B 0A 09 08
20h
07 06 05 04 03 02 01 00
1Fh
18h
Bank 3
17h
10h
Bank 2
0Fh
08h
Bank 1
07h
00h
Bank 0
Figure 46. Scratchpad Register Addressing.