Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 54
C1
C2
XTAL
XTALIN
BCLK/XTAL
BCLK
XTAL
PWDSEL.4
R1
Figure 44. Crystal oscillator input.
3. A user-provided logic signal supplies the oper-
ating clock frequency when applied to the
XTAL input pin. The XTALOUT pin should be
left unconnected, as shown in Figure 45.
BCLK/XTAL
XTALIN
Clock input signal
Leave
unconnected
Figure 45. Clock input from external system.
The device always powers up using the internal
oscillator, which serves as the system clock during
the system initialization phase. The system
switches over to the user selected clock source
sometime before the MCU starts executing the
application program. In most applications, the
user-defined clock source is the crystal-oscillator
clock (XTAL).
Two copies of the selected clock source propagate
in the CSoC. The BCLK signal is shared by all
dedicated resources connected to the CSI bus,
including the MCU, DMA, mappers, programmable
system decoders, etc. The CSL_BCLK propa-
gates into the CSL matrix and optionally connects
to programmable CSL “soft” modules and PIO pins.
Usually, the system clock source is selected at
design time and unchanged by software. However,
application code may need to modify the selection
if the crystal oscillator is turned off during power-
down mode. See "Power-On Reset Control" for
more information.
S
S
y
y
s
s
t
t
e
e
m
m
C
C
l
l
o
o
c
c
k
k
S
S
e
e
l
l
e
e
c
c
t
t
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
- -----
SCPU_
ENA
BCLK
SEL
76543210
Mnemonic: MISC Address: FE81h
MISC.7-2 are reserved locations that return 0
when read.
SCPU_ENA, when set, releases the CPU reset
caused when the SLAVE- input is Low. Used only
in Slave mode applications.
BCLKSEL, when set, selects the crystal oscillator
or an incoming, external clock source on the XTAL
input pin. When cleared, then the internal ring os-
cillator provides the system clock. When the
SLAVE- pin is Low, the BCLKSEL bit is forced to 1.
S
S
i
i
x
x
G
G
l
l
o
o
b
b
a
a
l
l
B
B
u
u
f
f
f
f
e
e
r
r
s
s
In addition to system clock, there are six global
signals available from within the CSL matrix. The
six signals, GBUF[5:0], are buffered and provide a
high-speed, low skew distribution path for addi-
tional clocks or high-fanout signals.
C
C
l
l
o
o
c
c
k
k
a
a
n
n
d
d
G
G
l
l
o
o
b
b
a
a
l
l
S
S
i
i
g
g
n
n
a
a
l
l
S
S
t
t
o
o
p
p
p
p
i
i
n
n
g
g
The system clock and the outputs from the six
global buffers can be optionally stopped during
power-down and debugging sessions.
B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
k
S
S
t
t
o
o
p
p
p
p
i
i
n
n
g
g
a
a
n
n
d
d
S
S
i
i
n
n
g
g
l
l
e
e
-
-
S
S
t
t
e
e
p
p
p
p
i
i
n
n
g
g
When stopped by a breakpoint event, the MCU
completes the current instructions before stopping
the bus clock, BCLK.
G
G
l
l
o
o
b
b
a
a
l
l
B
B
u
u
f
f
f
f
e
e
r
r
S
S
t
t
o
o
p
p
V
V
a
a
l
l
u
u
e
e
The six global buffers have a selectable value
when stopped. During design, each global buffer
is optionally configured to one of the following
functions.
1. Actively drive the global buffer, regardless of a
stop event.
2. Latch the last state of the global buffer and
drive the resulting value.
3. Force the buffer output Low.
8032 “Turbo” Microcontroller
Architecture
The 8032 "Turbo" microcontroller, embedded in
the Zylogic ZE5, is based on the standard 8032
device. The ZE5 is built around an 8-bit ALU that
uses internal registers for temporary storage and
to control peripheral devices. It executes the stan-
dard 8032 instruction set. A brief description of the
internal blocks follows.
A
A
L
L
U
U
The ALU is the heart of the 8032 microcontroller
and performs arithmetic and logical functions. It
also makes decisions for jump instructions, and
calculates jump addresses. The ALU is not di-
rectly user accessible, but the instruction decoder
reads the op-code, decodes it, and sequences the
data through the ALU and its associated registers
to generate the required result. The ALU primarily
uses the ACC, which is a Special Function Regis-
ter (SFR) on the chip. Another SFR, the B Regis-