Specifications

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Table 28. Estimated Parallel Initialization
Times at Various Bus Clock Frequencies.
Bus Clock Frequency
Device
1 MHz 5 MHz 25 MHz 40 MHz
ZE502 94 ms 19 ms 4.5 ms 3.1 ms
ZE505 112 ms 23 ms 5.2 ms 3.6 ms
ZE512 181 ms 37 ms 8.0 ms 5.3 ms
ZE520 265 ms 54 ms 11.4 ms 7.4 ms
ZE532 364 ms 73 ms 15.3 ms 9.9 ms
V
V
S
S
Y
Y
S
S
C
C
o
o
n
n
t
t
r
r
o
o
l
l
A power-on reset or other device-wide reset
causes the Zylogic ZE5 to start the initialization
process as shown in Table 39. The VSYS input
pin directs the system initialization state machine
how to behave should the initialization process fail
to find valid external initialization data.
If the VSYS pin is held High through the initializa-
tion phase and no valid configuration pattern is
found, then the CSoC automatically powers down
to conserve power. Another Power-On Reset or
System Reset event is required to restart the ini-
tialization process.
However, if VSYS is sampled Low during the ini-
tialization process, the CSoC will attempt to re-
start the initialization process following a failed ini-
tialization attempt. The initialization mode,
whether serial or parallel, is determined from the
PMOD pin. If VSYS is tied to GND, the CSoC will
attempt reconfiguring itself indefinitely until it finds
valid initialization data. This option might be useful
when the system operates in noisy environments.
In applications using a system supervisory chip, a
“VCC good” output from the supervisory device
can connect to VSYS, ensuring that initialization
only takes place when VCC is within the proper
operating voltage range.
If the MIU security bit is set, the VSYS level is ig-
nored and the CSoC will not access an external
memory via the MIU port.
Clocking and Global Signal Distribution
The Zylogic ZE5 configurable system-on-chip pro-
vides powerful, flexible clocking resources. A sys-
tem-wide bus clock (BCLK) provides clocking to
most of the ZE5 device. In addition, six global
buffers supply additional clocks or high-fanout sig-
nals for the CSL matrix.
S
S
y
y
s
s
t
t
e
e
m
m
c
c
l
l
o
o
c
c
k
k
s
s
e
e
l
l
e
e
c
c
t
t
(
(
B
B
C
C
L
L
K
K
)
)
The system clock, called BCLK, supplies the clock
to the 8032 “Turbo” microcontroller, its dedicated
resources, and to the CSI bus. Additionally, BCLK
is distributed globally to the CSL matrix and to the
PIO pins.
There are three potential user-defined sources for
BCLK.
1. An internal ring oscillator operates at frequen-
cies ranging between 5 MHz to 20 MHz, as
shown in Figure 43. The ring oscillator fre-
quency is temperature, voltage, and process
dependent. The internal ring oscillator can be
shut off during power-down mode by setting
the OSC bit (PWDSEL.3).
XTALIN
Leave
unconnected
BCLK
OSC
PWDSEL.3
Internal Ring
Oscillator
(~5 - 20 MHz)
Figure 43. Internal ring oscillator.
2. A crystal oscillator amplifier—connected inter-
nally between the BCLK/XTAL and XTALOUT
pins—supports 32 kHz operation and frequen-
cies from 2 MHz up to 40 MHz, as shown in
Figure 44. A crystal and the external circuitry
listed in Table 29 generate the desired fre-
quency. The crystal oscillator amplifier also
supports ceramic resonators. The crystal os-
cillator output can be turned off during power-
down mode by setting the XTAL bit
(PWDSEL.4). Frequencies above 24 MHz re-
quire the crystal to operate in the third over-
tone. The crystal operates in its fundamental
mode at lower frequencies. The internal feed-
back resistor should also be enabled using the
FastChip development system.
Table 29. Crystal Oscillator External
Component Values.
Crystal
Frequency
Range
Suggested
External
Resistor (R1)
External
Capacitor
(C1 and C2)
32 kHz
10 MΩ
10 pF
2 MHz—24 MHz
(fundamental)
1 MΩ
10 pF
24 MHz—40 MHz
(third overtone)
4.7 kΩ
10 pF