Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 52
There is unrestricted write access to this register, a
read is not required.
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- - - - - - MIU JTAG
76543210
Mnemonic: SECURITY Address: FF61h
SECURITY.7-2 are reserved bits and return a 0
when read.
MIU, when set, prevents any access through the
MIU port, including any microcontroller code fetch
to external memory. Once set, this bit can only be
cleared by turning off the power.
JTAG, when set, prevents any access through the
JTAG port. Once set, this bit can only be cleared
by turning off the power.
A write cycle to the security register must be pre-
ceded by two data-specific, back-to-back write op-
erations to the Protect register. A write operation
to the Protect register with a data pattern of AAh
must be followed by a write operation to the Pro-
tect register with a data value of 55h. Any write
cycle directed at a different CSI location or contain-
ing a different data pattern would reset the write
protect mechanism. After both write cycles are de-
tected in the right order and match the above-
specified data patterns, a write to the Security reg-
ister is enabled for a single write cycle.
The JTAG secure and MIU secure bits are active
high. Once set they can only be cleared by turning
off the power. The 8032 microcontroller can al-
ways read the security register to determine or
verify that the part is secured.
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The size of the initialization data file depends on
which ZE5 family device is used in the application
and the initialization method used.
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Each device has a predefined number of rows and
columns of initialization information as shown in
Table 26. The total data size is the product of the
number of rows and columns.
Table 26. Initialization Data Size.
Device Columns Rows Total Bytes
ZE502 102 120 12,240
ZE505 102 208 21,216
ZE512 144 296 42,624
ZE520 186 384 71,424
ZE532 228 472 107,616
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The secondary initialization program loads an ZE5
device with the initialization data. The initialization
program consists of 8032 instructions. The total
size of the secondary initialization data image for
parallel mode operation consists of
 967 bytes of 8032 instruction code to load the
initialization data into the ZE5 device
 19 bytes of initialization data header and footer
information
 the initialization data file from Table 26
 94 bytes of 8032 instruction code to set up the
data and code mappers after loading the ini-
tialization data.
Because the secondary initialization program al-
ways resides within the top 256 Kbytes of external
memory, aligned to a 16K boundary, the absolute
size of the data is larger than actual data file.
Table 27 shows the total size of the secondary
initialization data, including the initialization pro-
gram, and the memory requirements once the ini-
tialization data is aligned to a 16 Kbyte boundary.
Table 27. Parallel Mode Memory Requirements.
Device
Secondary Init.
Data Size
Total Memory
Requirements
ZE502 13,320 16K
ZE505 22,296 32K
ZE512 43,704 48K
ZE520 72,504 80K
ZE532 108,696 112K
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The time to initialize an ZE5 device depends on
the device used and the frequency of the bus clock.
After power-on or after RST- is asserted, the ZE5
device begins initialization clocked from the inter-
nal ring oscillator. The frequency of the internal
ring oscillator is minimum of 5 MHz and a maxi-
mum of 20 MHz. During the initialization process,
the bus clock source can be switched over to an
external clock source or to the crystal oscillator
amplifier, both of which operate up to 25 or 40
MHz, depending on the speed grade.
Table 28 shows the initialization time using various
frequency bus clock inputs. If bus clock is clocked
from the crystal oscillator amplifier, allow an addi-
tional 5 ms for crystal settling time. If using the
special 32 kHz mode for the crystal oscillator am-
plifier, allow 200 ms settling time.