Specifications

51 www.zylogic.com.cn
With the help of the microcontroller, the JTAG port
can also program an external Flash memory. In
the Flash programming mode, the JTAG unit
downloads program / erase / verify algorithms into
the internal RAM. The new Flash programming
data can also be stored in the internal RAM. After
the code and data mappers are properly defined
via the JTAG port, the 8032 microcontroller can
execute the program / erase / verify algorithms
required to write new data into an external Flash
memory device. The processor interacts with the
JTAG unit through flags and shared variables or
via interrupts.
S
S
l
l
a
a
v
v
e
e
M
M
o
o
d
d
e
e
In slave mode, the initialization data is downloaded
into the CSoC via a byte-wide, memory-mapped
interface, as shown in Figure 42. An external con-
troller, microprocessor, or a master Zylogic ZE5
device selects the slave CSoC by asserting the
CE- signal. Up to 18 address inputs are required
to initialize a single device. The address bus is
expandable up to 32 bits if required by the applica-
tion. The external controller presents address and
data, then strobes the WE- signal.
The master controller and the slave CSoC should
operate from the same external clock signal.
Once initialized, the master controller removes the
slave's internal reset by setting the SRST_DIS bit
in the slave's MISC configuration register. The
8032 microcontroller within the slave then begins
operation. However, a slave microcontroller is not
allowed to perform external code fetches. How-
ever, it can execute instructions downloaded by
the master controller into the slave's internal sys-
tem RAM.
Triscend E5
CSoC
(Slave Mode)
A[17:0] D[7:0] WE- OE- CE-
SLAVE-
PMOD VSYS
Memory Interface Unit (MIU)
A[x:18]
CE-
External Controller or
Master E5 CSoC
OE-WE-D[7:0]A[x:0]
(optional)
Upper Address
Application Dependent
(optional)
CE-
VCC
Figure 42. A slave mode interface to a Zylogic
ZE5 CSoC.
'
'
S
S
t
t
e
e
a
a
l
l
t
t
h
h
'
'
M
M
o
o
d
d
e
e
The CSoC has a security register allowing users to
block external accesses through the MIU port or to
prevent JTAG from executing CSI transactions.
This mode is most useful when the CSoC's internal
contents are battery-backed when power is re-
moved. In this mode, the initialization data is first
downloaded into the CSoC and the application
code stored and executed from internal system
RAM. Then the security bit is set, making the
CSoC's operation invisible to external probes.
When power is re-applied after the CSoC was in
secure mode and its contents battery backed, then
the CSoC begins executing from internal SRAM.
Blocking MIU accesses forces the 8032 "Turbo"
microcontroller to execute code only from the in-
ternal RAM. The executed program is prevented
from fetching external code or data through the
MIU port. Hackers cannot track the program flow
since the MIU port is disabled.
Blocking JTAG transactions on the CSI bus is es-
sential to prevent an external tester from reading
configuration and code stored inside the CSoC.
When JTAG security is set, boundary scan opera-
tions are still functional but bus transactions
through the JTAG unit are not functional. However,
the security status bit can be read through the
JTAG port.
System Reset events have no effect on the CSoC
once it has been secured. However, the applica-
tion reset sideband signal, RSTC, remains fully
functional in a secured CSoC. Following a RSTC
pulse, the CPU restarts its operation from program
location 0000H regardless of the security mode.
All MCU Reset events remain functional.
Once set, these security bits can only be cleared
by turning off the power. If the MIU security bit is
set, the VSYS system voltage monitor level is ig-
nored and the CSoC will not access an external
memory via the MIU port.
S
S
e
e
c
c
u
u
r
r
e
e
M
M
o
o
d
d
e
e
T
T
i
i
m
m
e
e
d
d
A
A
c
c
c
c
e
e
s
s
s
s
Mnemonic: PROTECT Address: FF60h
The Secure Mode Timed Access (PROTECT) reg-
ister controls the access to the ZE5's secure mode
bits. A separate timed access register (TA) con-
trols the protected bits within the 8032 "Turbo" mi-
crocontroller. To access protected bits, the user
must first write AAh to the PROTECT register.
This must be immediately followed by a write of
55h to PROTECT. This opens a window for three
machine cycles, during which time software can
write to these protected bits.
The PROTECT returns FFh when read, but this
register is rarely read.