Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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The serial memory interface requires only four in-
terface signals.
D0/SDIN - serial data bit from the serial PROM.
A0/SCLK - serial-clock supplied to the serial
PROM.
OE-/SRST - resets the serial memory to its starting
location when High and enables the serial data
output when Low.
CE- - serial chip enable.
The PMOD input pin must tied Low, indicating Se-
rial Mode initialization. Tying the SLAVE- pin High
ensures that the system starts up in a single chip
mode, configuring itself rather than relying on an-
other intelligent controller to provide initialization
data.
Following a power-on reset or a system reset, the
CSoC detects Serial Mode and starts downloading
initialization bitstream into the CSL. After the sys-
tem initialization phase, the application program is
serially loaded into the internal RAM.
Serial mode requires that application code reside
in the internal RAM. Once the user program is
resident in the system RAM, the 8032 "Turbo" mi-
crocontroller starts executing user code from loca-
tion 0000h, which is mapped to the internal system
RAM. At the beginning of user program execution,
code mapper C1 maps the entire 64K bytes of pro-
gram space into the internal system RAM. How-
ever, the data mapper values must be handled by
application code.
During the serial download phase, all PIO and MIU
pins not active during the serial initialization proc-
ess are pulled High by weak pull-up resistors. Af-
ter initialization, these pins perform as described in
the logic design.
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The JTAG mode initializes the Zylogic ZE5 using
an external tester, personal computer (PC), or
other intelligent host. The JTAG port is also useful
for debugging application code or to program ex-
ternal memory devices via the MIU port. When a
PC acts as a host, the JTAG unit is controlled by a
series of commands entered from the Zylogic
FastChip development system or third-party hard-
ware debugger.
Triscend E5
CSoC
A[17:0] D[7:0] WE- OE- CE-
SLAVE-
PMOD VSYS
TMSTDOTDI TCK
Memory Interface Unit (MIU)
JTAG Unit
A[x:18]
CE-
External Tester or
Host PC
External Parallel Memory
(Optional)
OE-WE-D[7:0]A[x:0]
VCC
(optional)
Upper Address
Application Dependent
CE-
Figure 41. A JTAG interface to the Zylogic ZE5.
External memories are not required in JTAG con-
figuration mode. The JTAG link can directly initial-
ize the CSL matrix, download the necessary appli-
cation code into the internal RAM, assign values to
the data and code mappers and direct the 8032
microcontroller to execute code from the internal
system RAM.
Since the JTAG unit can serve as a system de-
bugger in this operating mode, any type of external
memory device is allowed.
Figure 41 depicts a typical JTAG interface to a Zy-
logic ZE5. In the figure, the CSoC is already con-
nected to an external parallel memory. The JTAG
port is compliant with IEEE standard 1149.1. The
four JTAG pins are dedicated only to the JTAG
function.
TCK – Test clock input. If unused should be tied
high.
TMS – Test mode select input. If unused should
be tied high.
TDI – Test data input. If unused should be tied
high.
TDO – Test data output.
The JTAG unit also serves as a master on the CSI
bus and can read and write every addressable en-
tity in the system.
The JTAG port optionally controls the 8032 "Turbo"
microcontroller by setting breakpoint events that
freeze the MCU. Once the processor is frozen, the
JTAG unit can single-step the processor, examine
the internal registers of the processor, and then
resume the processor operation.