Specifications

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executed from internal RAM, offering faster access
plus security in battery-backed applications.
The majority of the system, including the microcon-
troller, operates from a single bus-clock signal.
Optional sources for the bus clock include driving it
directly from an off-chip signal, connecting an ex-
ternal crystal or ceramic oscillator between the
dedicated crystal-oscillator amplifier pins, or using
the internal ring oscillator. Six other global buffers
provide high-fanout signals to CSL functions. The
bus clock and the global buffers can optionally be
stopped upon a breakpoint event and shut off dur-
ing power-down mode.
Power management control provides selectable
power-down options over internal functions. Fur-
thermore, each PIO provides pin-by-pin power-
down settings.
The ZE5 configurable system-on-chip, like other
advanced processors, is built from leading-edge
static CMOS technology. The ZE5 device is infi-
nitely in-system programmable. A power-on reset
circuit guarantees proper start-up operation after
power is asserted. There are various initialization
(bootstrapping) modes to support different applica-
tion requirements. The ZE5 can load itself auto-
matically after power-on from an external, byte-
wide boot memory. Optionally, the ZE5's configu-
ration data is stored in a serial sequential-access
PROM. In serial mode, the user's code is copied
to and executed from the internal SRAM. Serial
mode frees a number of device pins so that they
can be used as user-defined PIO pins.
In security-conscious applications, the user's pro-
gram is stored in internal RAM and battery-backed
using external circuitry. If the ZE5 configurable
system-on-chip is in ‘stealth’ mode, it boots from
internal RAM when VCC is re-applied after battery
back up. Stealth mode optionally disables the
JTAG interface port and disables external fetches
via the MIU.
An internal initialization boot ROM controls the
start of initialization during power-on after the RST-
pin is released. The primary purpose of the initiali-
zation boot ROM is to find the user's initialization
data and code stored in the secondary boot code,
usually held in PROM.
Initialization programs can also be downloaded
directly to internal SRAM through the JTAG port.
Likewise, initialization programs can be written to
external flash via JTAG through the MIU interface.
Besides downloading initialization programs, the
JTAG port offers nearly full access to the micro-
controller, peripherals, and CSL functions to aid in
debugging. The JTAG interface can become a bus
master on the internal CSI bus. During system
debugging, the JTAG port also sets up the internal
hardware breakpoint unit.
The hardware breakpoint unit contains two func-
tions that monitor the 8-bit read or write data bus,
the 32-bit internal address bus, control signals and
the type of processor instruction (code or data ac-
cess). Upon a predefined set of conditions, the
breakpoint unit halts execution of the application
program. Via JTAG control, the user can single-
step instruction execution of the processor.
Together, the 8032 "turbo" microcontroller, its dedi-
cated peripherals, the on-chip RAM, the internal
CSI system bus, and the CSL matrix and PIOs
form a powerful, integrated configurable system.
8032 "Turbo" Microcontroller
The Zylogic ZE5 8032-based configurable system-
on-chip is fully instruction set compatible with other
industry-standard 8032/8051 microcontrollers. It
includes the resources of the standard 8032 in-
cluding three 16-bit timer/counters; a full-duplex
serial port and twelve interrupt sources with three
priority levels.
The ZE5 features a performance-enhanced 8-bit
CPU with a redesigned core processor, reducing
unnecessary clock and memory cycles. The in-
struction cycle of a standard 8032 is twelve clock
cycles while the Zylogic ZE5 reduces this to four
clock cycles for the majority of instructions, thereby
improving performance by an average of 1.5 to 3
times.
This naturally speeds up the execution of the in-
structions. Consequently, the ZE5 offers more
processing power compared to the original 8032,
even using the same frequency crystal. For a
given throughput, the ZE5 can be operated from a
lower-frequency clock than the original 8032, re-
ducing power consumption.
The ZE5 also provides dual Data Pointers (DPTRs)
to boost block data memory transfers.
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The original 8032 offers up to four 8-bit ports, a
total up to 32 lines. In the ZE5, the 8032 proces-
sor core is embedded with other functions. The
processor optionally connects to as many PIO pins
as required by the application.
U
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The Zylogic ZE5's UART is a superset of the
UART in the original 8032 family, though offers
timing compatibility. The UART provides en-
hanced features such as automatic address rec-
ognition and frame error detection.