Specifications

49 www.zylogic.com.cn
Slave Passive
Downloaded by
other controller
through bus inter-
face.
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Parallel mode initialization, as shown in Figure 39,
enables the user to store and execute application
programs from a standard, byte-wide external
memory. System configuration is also stored in
the external memory. System initialization time is
much faster relative to serial configuration because
user application programs are typically not
downloaded to internal system RAM.
The MIU signals are:
D[7:0] – the eight-bit data bus from the external
memory.
A[17:0] – the lower 18 bits of the address bus. If
additional address bits are required, the upper ad-
dress lines—A18 and beyond—can be enabled in
the user’s design.
WE- - write enable signal provided to writeable
memories such as Flash, EEPROM, and SRAM
OE- - enables the data output from the external
memory during a read operation.
CE- - chip enable to the external memory.
Triscend E5
CSoC
A[17:0] D[7:0] WE- OE- CE-
SLAVE-
PMOD VSYS
Memory Interface Unit (MIU)
A[x:18]
CE-
External Parallel Memory
OE-WE-D[7:0]A[x:0]
VCC
(optional)
Upper Address
Application Dependent
(optional)
CE-
Figure 39. Parallel-mode initialization.
PMOD is optionally pulled up to VCC. If left un-
connected, PMOD powers on with a weak pull-up
resistor, pulling the pin High during the initialization
phase.
Address lines A[17:0] sufficiently address up to
256K bytes of external memory. If a larger mem-
ory device is used, additional optional address
lines serve as high-order address lines. Even
though the 8032 can only directly access 64K
bytes of code space, the Zylogic ZE5 provides
more code space by using code mappers that dy-
namically change the 8032’s base address. The
external parallel memory can also contain data
arrays such as look-up tables. Using data map-
pers, the external memory can also be mapped to
the external data memory of the processor.
Once the system initialization is complete, the
8032 microcontroller starts executing application
code from location 0000h, which is mapped to the
external memory. Parallel mode requires that at
least some application code reside in external
memory. At the beginning of application program
execution, code mapper C1 maps locations 0000H
– 7FFFH of program space into the external mem-
ory. The user application code must initialize the
data mappers and code mappers.
During the parallel initialization phase, all PIO and
MIU pins that do not participate in the parallel
memory interface, are pulled High by weak pull-up
resistors. These pins are properly initialized to
their user-defined configurations at the end of ini-
tialization.
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In serial initialization mode, the initialization data
and user code are stored in a sequential-access
serial PROM, similar to the devices used to pro-
gram FPGA devices. Sequential-access serial
PROMs are distinct from I
2
C- or SPI-format serial
PROMs, as they are not addressable and are typi-
cally much higher density.
Serial initialization mode frees most of the memory
interface unit (MIU) pins so that they can be used
as PIO pins in the user's design. Figure 40 shows
the connections between the Zylogic ZE5 config-
urable system-on-chip and the serial memory.
Triscend E5
CSoC
A0/SCLK D0/SDIN OE- CE-
SLAVE-
PMOD VSYS
Memory Interface Unit (MIU)
CE-
External Sequential-Access
Serial PROM
OE-/
RESET
DATACLK
CE-
Application Dependent
CE-
VPP
VCC
VCC
CEO-
to cascade serial PROMs
Figure 40. Serial-mode initialization.