Specifications

47 www.zylogic.com.cn
The JTAG port can also be used to initialize the
CSoC or to update external memory devices con-
nected to the MIU port. Using external Flash
memory, the JTAG unit downloads a Flash-
programming algorithm to the CSoC’s internal
RAM. It then interacts with the internal MCU, al-
lowing the processor to control the actual program
/ erase / verify algorithms while the JTAG port sup-
plies new data for programming or new series of
commands required by the MCU.
D
D
e
e
b
b
u
u
g
g
g
g
i
i
n
n
g
g
S
S
u
u
p
p
p
p
o
o
r
r
t
t
S
S
y
y
s
s
t
t
e
e
m
m
R
R
e
e
q
q
u
u
i
i
r
r
e
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m
m
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n
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s
s
Unlike debuggers for traditional 8051 designs, the
ZE5 debugging environment does not require any
additional system resources. The ZE5 environ-
ment does not use any additional code space nor
does it consume a serial port. All debugging inter-
action is through the dedicated four-pin JTAG con-
nection.
The recommended debugging header, shown in
Figure 38, connects to the Zylogic JTAG
Download/Debug cable. The header uses
through-hole stake-pins on 0.1 inch centers.
GND
2019
1817
+5 VDC Out
N.C. N.C.
1615
GNDN.C.
1413
N.C.N.C.
1211
GND
System Reset
(open collector)
109
TMS N.C.
87
TCK N.C.
65
N.C.
+3.3 VDC Out
(indicator only)
43
21
TDI
TDO
N.C.
N.C.
(Top View)
Figure 38. Zylogic ZE5 Download/Debug Cable
Header.
Likewise, no special in-circuit emulator (ICE) is
required. The ZE5's on-chip breakpoint unit pro-
vides the capabilities available in most ICE sys-
tems.
Debug Host System
Freeze
Interrupt
Reset
Interrupt
JTAG
Interface
Configurable System-on-Chip
User
Code
External Memory
Initialization
Data
CSI BUS
(addess,data,control,arbitration)
MIU
Bus Reset
DMA Req
DMA Ack
DMA
Controller
JTAG
Controller
Internal
SRAM
8032
"Turbo"
MCU
Breakpoint
Logic
CSL Logic
Clock
Disables
Figure 37. System debugging block diagram.