Specifications

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Mnemonic: XMAP_TAR_1 Address: FE21h
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A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: XMAP_TAR_2 Address: FE22h
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A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: XMAP_ALT Address: FE24h
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Table 23 shows the default assignment for higher
address bits in each of the mappers. These values
are loaded into the mapper registers during the
initialization process.
The Zylogic FastChip development system uses
these default values when assigning the 32-bit
physical addresses for the CSL address selectors.
These values and the mapper registers them-
selves allow CSL address selectors to selectively
respond to different instruction types.
For example, if a Flash memory device is con-
nected to the MIU, some addresses can be ac-
cessed as code or data segments. During normal
operation, the Flash segment is typically used to
store code. However, during a programming ses-
sion, the Flash memory is regarded as a data
segment. This differentiation between code and
data using high order address lines distinguishes
between code and data accesses to the same
physical address.
In another example, assume that an address se-
lector is used to enable off-chip ROM for external
code storage. Code mapper C1 might point the
ROM. The selector would need to respond to both
operand and op-code fetches. Because
CMAP1_TAR_2 = 00101000b and CMAP1_ALT =
000010000b, FastChip will program the upper byte
of the selector's MASK register with 0010000,
making the selector respond to both operands and
op-code fetches.
Table 23. Default Values for Higher-Order Ad-
dress Mapper Registers.
Transaction
Type Register Name
Default
Value
A[31:24]
C2 Operand
Fetch
CMAP2_TAR_2 30h
C2 Op-Code
Fetch
CMAP2_ALT 50h
C1 Operand CMAP1_TAR_2 28h
Fetch
C1 Op-Code
Fetch
CMAP1_ALT 48h
C0 Operand
Fetch
(Init. ROM)
CMAP0_TAR_2 20h
C0 Op-Code
Fetch
(Init. ROM)
CMAP0_ALT 40h
D3 Data
(CRU Regis-
ters)
DMAP3_TAR_2 98h
D5 Data DMAP5_TAR_2 A8h
D4 Data DMAP4_TAR_2 A0h
D2 Data DMAP2_TAR_2 90h
D1 Data DMAP1_TAR_2 88h
D0 Data DMAP0_TAR_2 80h
SFR Latch XMAP_ALT E0h
SFR Pin XMAP_TAR_2 C0h
The mapper values are also used during debug-
ging allowing the hardware breakpoint unit to dis-
tinguish between operand and op-code fetches
The distinction between SFR pin and SFR latch
transactions is required only if the designer selects
8032-compatible PIO ports from Zylogic "soft"
module library. The 8032 microcontroller has in-
structions that treat 8032 PIO ports differently than
their respective SFR. In applications, there is no
need for CSL address selectors to distinguish be-
tween SFR latch and SFR pin instructions.
System Debugger
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A PC acting as an external tester or debugger can
interface with the Zylogic ZE5 configurable system-
on-chip via its JTAG port, using a cable connected
between the PC parallel port and the target board,
as shown in Figure 37.
The JTAG unit can access all addressable system
resources by becoming the bus master on the in-
ternal CSI bus. Serving as a bus master, the
JTAG unit converts serial bitstreams into parallel
registers whose contents are placed on the ad-
dress, data and command buses to emulate CSI
bus transactions. A JTAG master also directly ac-
cesses internal MCU registers and CSL configura-
tion data with visibility to functions not accessible
from application programs.
Furthermore, the JTAG unit can hold the MCU in
reset by asserting the J_RESET command or hold
the entire system in reset using the FORCE_BRST
and FORCE_NOBRST. The JTAG unit also inter-
acts with the MCU using an interrupt handshake